National Semiconductor Corporation

Other

Silicon Valley Group, Inc.

Don Roy Sauer

Kwok-Fu Chiu

Alexander H Slocum

Matthew J Van Doren

Tim D Isbell

Johann Tam

Fred T Cheng

Rodney Scott Ziegenhagen, Ii

Dale A Oakeson

Larry Gerszewski

S Chen Sean

David Pap Rocki

William A Cocke

The harvesting Resistor consists of single or dual supply DC to DC converter, which has a current sense resistor in series with its output port. The sensed current magnitude is coupled back to modulate the duty cycle in a way such that a voltage to current together with the power absorbing relationship of a resistor is appearing at the DC to DC converter's output port. Such an emulated resistor, when connected to an external power source, can efficiently transfer the absorbed energy from an external power source to the single or dual supplies of the DC to DC converter.

Energy harvesting resistor

A split supply DC to DC converter is coupled through a low resistance path to a secondary coil of an ac line transformer, and is used as a high efficiency bidirectional AC to DC convertor. A small sense resistor is placed in series with the secondary in order to measure secondary current. The duty cycle of the DC to DC converter, which defines the voltage of what is normally treated as an output node, is modulated by the monitored secondary current. By coupling such an output node across the secondary coil, a voltage to current relationship is defined across the secondary to be that of a simulated resistor. Such a resistor will absorb power from the AC line and transfer it efficiently to the split supplies. The power transfer direction is reversed with the same efficiency by defining the current to voltage relationship to be one of a negative resistor.

Rectifier less bidirectional AC to DC converter

A Folding Comparator circuit which receives an analog input current and both compares it to a DC reference current while at the same time folding the input current around the reference current to be passed on as an output current which can then be passed on to another folding comparator stage. A series of such stages connected together with some XOR logic gates can perform an analog to digital conversion process as a pipeline of auto-folding stages which will instantly convert analog signal to digital signal.

Folding comparator compatible with level-crossing sampling

Operational transconductance amplifiers have a natural signal capacity format in which signal performance can be expressed in terms of fixed percentages. Input signal can be applied to Operational transconductance amplifiers in this natural signal capacity format in order to optimize performance. A signal which drives a given Operational transconductance amplifier architecture to produce an output current which is at 50% of it's maximum available output current can be thought of as applying an input voltage which is at 50% of an Operational transconductance amplifier's maximum input voltage capacity. In this input/output channel capacity format, dc offset, distortion, and noise all are temperature independent. By translating input signal between a voltage format to a channel capacity format using the methods of this invention, output signal performance attributes such as gain, frequency response, dc offset, temperature drift, distortion, and noise, can all be optimize over the full temperature range for all types of Operational transconductance amplifier architectures and applications.

Transconductance signal capacity format

A linearized bipolar differential input stage that contains two high gain current mirrors coupled in series with the input voltage signal through the input transistors to allow the output differential current to greatly exceed the DC output current in a Class AB fashion. The extended output current range over and above the DC current significantly lowers the percentage of effects for both DC offset and noise in the output signal path. Non-linearity cancellation is also optimized for the lowest level of input distortion through adjusting transistor area ratios.

Linearized class AB biased differential input stage

A ring device is adapted for wearing on at least one finger of a user. The ring device includes a wearable main body portion and an optical member that is moveably affixed thereto. The optical member can be positioned in at least two positions: a viewing position, and a storage position. The optical member may be moved relative to the main body portion through a number of positioning mechanisms including: a hinged member, a sliding member, and a rotating member. The viewing position may include any number positions for viewing an object in a field of view. The storage position corresponds to an alignment of the optical member with the main body such that the device is aesthetically pleasing. A face of the main body may include an insignia or other decorative design that is viewable through the optical member, and may optionally be removable by the user.

Ring device with optical focusing mechanism

A voltage reference circuit is arranged in a CMOS process based technology to provide a configurable voltage reference. The voltage reference includes bipolar transistors that are implemented as parasitic devices in the CMOS process. Two of the bipolar transistors are configured to generate a &Dgr;Vbe signal in the voltage reference circuit. An error amplifier cooperates with the two bipolar transistors via a control signal such that the control signal is related to &Dgr;Vbe/R. A first current source is coupled to another bipolar device, which is parallel connected to a resistor divider. The output of the resistor divider provides a divided reference signal that is related to the Vbe of the other bipolar device. Another resistor is coupled between a second current source and the output of the resistor divider such that an adjustable/temperature compensated reference signal is provided.

CMOS adjustable bandgap reference with low power and low voltage performance

A Sauer diode circuit is arranged to introduce a signal into a circuit to compensate for mismatch effects to various parameters in a current mirror circuit. Current matching between transistors is improved by providing matched errors such as forward current gain (Beta), early voltage, transconductance, channel-length modulation, as well as other sources of matching errors. The Sauer diode includes a series of transistors that are arranged to operate as a diode circuit that has errors that are matched to other components in an application circuit. Example application circuits include, but are not limited to reference circuits, operational amplifiers, comparators, analog-to-digital converters, digital-to-analog converters as well as other circuits that employ current mirror circuitry. The Sauer diode may be implemented in a single transistor technology such as MOS, BJT, FET, or a number of mixed technologies such as BiCMOS, BiFET and the like.

Method and apparatus for improving current matching in an electronic circuit

An output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced.

CMOS assisted output stage

A method and apparatus is directed to generating an oscillation frequency utilizing the thermal heat transfer properties of semiconductor material as a feedback loop in an oscillator. The oscillator includes a comparator that compares two input signals and enables one of two heater circuits. Each heater circuit is thermally coupled to a sensor and reference circuit. Each sensor and reference circuit pair is arranged such that the reference circuit is heated while the sensor cools. The combination of each sensor and reference circuit produces input signals for the comparator. The frequency of the oscillator is determined by the heat transfer rate between the heater circuit and the corresponding sensor, and the thermal cooling rate of the other sensor. Changing the biasing currents, and distances between the heat sources and the thermal sensors adjust the duty cycle and frequency.

Apparatus and method for a thermal feedback oscillator

A translation circuit for transferring a differential voltage to a ground referenced voltage includes a differential input circuit, a sample/hold (S/H) circuit, and a compensation circuit. The S/H circuit includes a S/H capacitor, a series capacitor and a switch. The S/H and series capacitors are connected in series between an output line and a source of ground potential (GROUND). The switch shorts the bottom electrode of the S/H capacitor to GROUND when executing a translation operation. The differential input circuit receives the differential voltage and selectively provides the differential voltage across the S/H capacitor so that the top and bottom electrodes of the S/H capacitor have voltages V&plus; and V&minus;, respectively. Parasitic capacitance tends to add charge to the S/H capacitor during the translation operation. The compensation circuit compensates for parasitic capacitance by removing, ideally, the same amount of charge from the S/H capacitor by the end of the translation operation.

Method and apparatus for transferring a differential voltage to a ground referenced voltage using a sample/hold capacitor

A method and apparatus is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors. The level shifting buffer amplifiers are also arranged such that the gate of each output transistor is selectively switched to a power supply voltage, providing maximum gate drive to the output transistor when the output transistor drives a maximum current to an external load. A single capacitor may be employed to provide compensation between the output of the amplifier and the output of the class AB turnaround stage. The sub-threshold operation of the level shifting buffer amplifiers permits the output stage amplifier to operate on power supplies down to roughly a single transistor threshold voltage.

Single cell rail-to-rail input/output operational amplifier

An integrator circuit having a relatively large RC time constant includes a resistive element implemented with a field effect transistor operated in a sub-threshold mode. The size of the field effect transistor is selected, in addition to the sub-threshold gate voltage, to achieve a desired resistance value in a small area and without using bipolar devices. A differential integrator circuit includes two field effect transistors operated in a sub-threshold mode, with a capacitor connected between the output terminals of the two field effect transistors. A bulk drive circuit can be optionally used to reduce high frequency in the bulk.

Sub-threshold CMOS integrator

A single cell voltage reference operates under low power supply requirements to provide a configurable voltage reference. The single cell voltage reference includes a diode device that is biased as a voltage source. Two series connected resistive devices are connected in parallel with the diode device. The diode is biased with a current that is proportional to delta Vbe/R, such that the impedance of the diode tracks R. Another current source that is also proportional to delta Vbe/R is provided at the junction of the two resistors such that the voltage across one of the two resistors may be employed as a reference voltage that is less than 1.2V. The ratio of the resistors and scales the reference voltage level. Voltages that are below 1.2V are provided that are temperature compensated similar to a band-gap reference. The diode voltage as driven by a current source determines the lower limit of the reference voltage. The reference voltage may be combined with a buffer or an operational amplifier such that a regulated supply can be provided that is below 1.2V. Metal masks may be arranged to permit reconfiguration of the voltage reference cell for use above 1.2V, or to change the regulation voltage without redesigning the voltage reference cell.

Method and system for generating a low voltage reference

A method and apparatus is directed to a thermal shut down for a low drop out (LDO) regulator including a MOS transistor. An error amplifier controls the gate of the MOS transistor by comparing the regulator output voltage to a reference voltage that is generated by a reference circuit. To enhance power supply rejection and improve regulation, the error amplifier and the reference circuits are powered by a potential at an internal power supply node. A power control circuit selectively couples the internal power supply node to one of the regulated output voltage and the unregulated supply voltage. A start-up circuit may be employed to ensure that regulation begins when power is applied. A temperature sensor circuit detects when the operating temperature exceeds a predetermined temperature and activates a supply transfer circuit to couple the unregulated supply to the internal power supply node. After the internal power supply node reaches the unregulated power supply potential, a shutdown circuit deactivates the MOS transistor. A diode is coupled between the regulator output and the internal power supply node to prevent current flowing from the internal power supply node to the load when the over-temperature condition exists. A transistor mirror may be configured to couple the unregulated supply voltage to the internal power supply node when activated. The thermal characteristics of a transistors threshold voltage may be employed as a temperature sensor. Another transistor may deactivate the MOS transistor by coupling the gate of the MOS transistor to the unregulated supply voltage.

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San Jose, CA, United States of America

Don Roy Sauer