Bell Telephone Laboratories

At&t Bell Laboratories

Don R Draper

James M Grinn

David J Brahm

Peter Kusulas, Jr

Christopher Edmonds

In a processor system having a central processor and secondary support processor mounted on a backplane board, a separate peripheral interrupt bus is provided for each secondary support processor to give full interrupt priority capability to peripheral devices connected to the support processors. The support processors (110, 120) and certain of the system's peripheral interface circuits (102, 104) are connected to the system's central processor (101) via a primary interrupt bus (105) and other peripheral interface circuits (112, 114, 122) are connected to their associated secondary processors (110, 120) via separate interrupt buses (115, 125) all on the same backplane board. The backplane board is divided into an upper section and a lower section and the primary interrupt bus and the interrupt request and acknowledge terminal pins for all circuit boards are in the lower section. The secondary processor boards and interface circuit boards served by the central processor have interrupt request and acknowledge terminal pins connected to the primary interrupt bus in the lower section. The interrupt request and acknowledge terminal pins for any peripheral interface circuit served by a secondary processor are connected to the associated secondary processor via a secondary interrupt bus formed in the upper section of the backplane and conductors extending between the sections.

Interrupt bus structure

A circuit for the detection of write errors in a memory with selectable byte addressing. The memory is capable of selectively writing bytes within a memory word by decoding control signals and address signals received from a processor. The decoder and transmission path of the control signals are checked by the processor generating incorrect parity for the bytes which are not to be written. The memory decodes the control signals, checks the parity of the bytes, and generates a write parity error if the decoder selects a byte with incorrect parity to be written. If the memory malfunctions and spuriously writes an unselected byte, this fact will be detected when the unselected byte is read. The memory checks each byte read for parity, and incorrect parity causes the memory to transmit a read memory error to the processor.

Memory write error detection circuit

A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by corresponding ranges of memory access addresses. Each table entry comprises one or more access control bits and associated data. Each table address defines a control location in one memory of the plurality and data locations in additional memories of the plurality. An entry to be written into the table is provided to input rotate circuitry which is controlled by a portion of the table address which defines the location at which the entry is to be written. The input rotate circuitry delivers the access control bits of the entry to a memory in which a control location is accessed and delivers the associated data bits to additional memories in which data locations are accessed. When an entry is read from the table, the address corresponding to that entry is utilized to access the control and data locations containing the entry. An entry read from the table is provided to output rotate circuitry which is controlled by a portion of the table address which defines the location from which the entry is read. The output rotate circuitry reassociates the access control bits and the associated data bits to their original format. To rapidly clear the memory locations which can contain access control bits, all memory addresses which define control locations are sequentially accessed in parallel in all memories of the plurality. An address generator which defines the memory addresses at which control bits can be stored is stepped sequentially through those addresses and as each address is utilized, the control bits at those locations are cleared. Accordingly, a control location is simultaneously cleared in each of the memories of the plurality thereby dividing by the number of memories the time necessary to clear the table locations which can contain access control bits.

Growing community of inventors

Lisle, IL, United States of America

Don R Draper