Intel Corporation

Don Newell

Ravishankar Iyer

Jaideep Moses

Ramesh Kumar Illikkal

Tryggve Fossum

Li Zhao

Erik J Johnson

Srihari Makineni

A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

Priority based throttling for power/performance quality of service

In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.

Selective storage of data in levels of a cache memory

A method includes extracting packets from within a received frame, generating digests of the extracted packets, and hashing the generated digests.

Framer

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Portland, OR, United States of America

Don Newell