Telasic Communications, Inc.

Hughes Aircraft Company

Raytheon Company

Microelectronics Technology, Inc.

Don C Devendorf

Lloyd Frederick Linder

Erick M Hirata

Matthew S Gorder

Khiem V Cai

David B Rutan

Edwin A Kelley

Ricky Y Chen

Ahmad Khanifar

Benjamin Felder

Clifford Duong

Wade J Stone

Kikuo Ichiroku

Eugene Baskevitch

Dung C Nguyen

Soon Yoon

Michael Naone Farias

Louis E Gates, Jr

Kenneth Alan Essenwanger

Clifford W Meyers

Kelvin T Tran

William W Cheng

Kelvin Tran

Roger N Kosaka

Robert T Narumi

Seth L Everton

James R Gaskill, Jr

Samuel Davis Kent, Iii

Hieu M Le

Michael H Liou

Christopher B Langit

Phung N Phan

Albert Kamensky

Roy S Komori

Bruno W Garlepp

Bo S Hong

Louis F Linder

Cuong D Tran

A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency.

System and method for dynamic drain voltage adjustment to control linearity, output power, and efficiency in RF power amplifiers

A system and method for stabilizing a coefficient set used by a digital predistortion (DPD) engine to apply pre-distortion to a transmit signal and cancel distortion generated by a distorting element or distorting system when transmitting the transmit signal, including obtaining an initial coefficient set; rotating the initial coefficient set to maintain a phase of fundamental components (w(t), . . . , w(t)) of the initial coefficient set as a constant value; averaging in the time domain the rotated coefficient set to obtain an averaged coefficient set; applying the averaged coefficient set to the DPD engine, the initial coefficient set expressed in a first equation [27]; computing the phase of the fundamental components of the initial coefficient set with a second equation [28]; and computing the rotated coefficient set with a third equation [29].

Digital pre-distortion technique using nonlinear filters

A method and computer program product for operating a linearizer for a circuit, including generating a set of coefficients via a characterizer; predistorting a signal input to the circuit responsive to the coefficients and generating a linearized output in response thereto; filtering the signal through a linear digital filter having linear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; generating powers of the signal; inputting the generated powers of the signal through tapped delay lines, each line having nonlinear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; applying the coefficients to the linear and nonlinear digital filter taps; summing each of the nonlinear digital filter taps corresponding to a certain number of delay units; and adding the sum of each of the delay units to a particular linear digital filter tap.

A crest reduction system and method. The inventive system includes a first circuit for suppressing peak amplitudes of an input signal and providing a peak amplitude suppressed signal in response thereto and a second circuit coupled to the first circuit for rejecting intermodulation distortion in the amplitude suppressed signal. In the illustrative implementation, the first circuit is a peak amplitude suppressor having circuitry for computing an amplitude of the input signal and for computing a gain factor for the input signal in response thereto. In the best mode, the gain factor is obtained from a lookup table. The peak amplitude suppressor further includes a multiplier for applying the gain factor to the input signal. In the illustrative embodiment, the second circuit includes a plurality of bandpass filters and a summer for combining the outputs thereof.

System and method for crest factor reduction

A system, method and computer program product for stabilizing a coefficient set used by a digital predistortion (DPD) engine to apply pre-distortion to a transmit signal and cancel distortion generated by a distorting element or distorting system when transmitting the transmit signal, including obtaining an initial coefficient set; rotating the initial coefficient set to maintain a phase of fundamental components (w(t), . . . , w(t)) of the initial coefficient set a constant value; averaging the rotated coefficient set to obtain an averaged coefficient set; and applying the averaged coefficient set to the DPD engine.

Digital pre-distortion technique using non-linear filters

A linearizer and method. In a most general embodiment, the inventive linearizer includes a characterizer coupled to an input to and an output from said circuit for generating a set of coefficients and a predistortion engine responsive to said coefficients for predistorting a signal input to said circuit such that said circuit generates a linearized output in response thereto. In a specific application, the circuit is a power amplifier into which a series of pulses are sent during an linearizer initialization mode of operation. In a specific implementation, the characterizer analyzes finite impulse responses of the amplifier in response to the initialization pulses and calculates the coefficients for the feedback compensation filter in response thereto. In the preferred embodiment, the impulse responses are averaged with respect to a threshold to provide combined responses. In the illustrative embodiment, the combined responses are Fast Fourier Transformed, reciprocated and then inverse transformed. The data during normal operation is fed back to the data capture, corrected for distortion in the feedback path from the output of the amplifier, converted to basedband, synchronized and used to provide the coefficients for the predistortion linearization engine. As a result, in the best mode, each of the coefficients used in the predistortion linearization engine can be computed by solving the matrix equation HW=S for W, where W is a vector of the weights, S is a vector of predistortion linearization engine outputs, and H is a matrix of PA return path inputs as taught herein.

A low distortion amplifier. The novel amplifier includes a first transistor Qhaving first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Qhaving first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q, wherein the second output terminal of Qis connected to the second output terminal of Qin order to eliminate a nonlinear current component in Q. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q, Qfor holding the second output terminals of Qand Qat a desired voltage to further reduce distortion and to maintain a wide bandwidth.

Low distortion amplifier

A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.

DNL/INL trim techniques for comparator based analog to digital converters

A high speed switch. The novel switch includes an input circuit having a transistor Qfor receiving an input signal, a first mechanism for providing a path from an output of Qto an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Qto a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

High speed switch

A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.

Sample and hold circuit and bootstrapping circuits therefor

A signal processing system and method. The inventive system includes a first circuit for distributing an input signal between two or more channels in a current mode of operation. A second circuit is disposed in each of the channels for processing the input signal and providing an output signal in response thereto. A third circuit is provided to combine the signals output by the processing circuit. A fourth circuit is included for controlling the first and the third circuits. In a specific illustrative embodiment, the system further includes a radio frequency stage for downconverting a received signal and providing the input signal in response thereto. In the specific embodiment, the first circuit includes a mixing circuit. The mixing circuit includes Gilbert cells and circuitry for providing automatic gain control for each of the channels individually. The Gilbert cells and the automatic gain control circuitry are driven by a transconductance amplifier and therefore operate in a current mode. Differential digital automatic gain control signals are provided in response to a channel select signal from a digital control circuit. The inventive circuit provides multiple IF channels which may be filtered individually. The invention thereby provides wide band operation in a simple, single stage implementation that consumes little power. Further, the current mode thereof is effective in the reduction of insertion loss.

Low noise, low distortion, muxable Gilbert mixer signal processing system and method with AGC functionality

A DAC () including an operational amplifier () having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I/2 -I/2); and an arrangement () for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC () further includes a first resistive element (RR) disposed in each of the current paths, a second resistive element (R-R) disposed between the current paths, and a feedback resistor (R) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW-SW); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths. The invention is adapted to lower the distortion of digital to analog converters by improving differential nonlinearities and integral nonlinearities, caused primarily by current source gradient errors, without the need for trimming.

Split cell bowtie digital to analog converter and method

A system and method for sampling and holding a signal. The invention includes a novel input circuit for a track and hold circuit comprising a circuit Q for receiving an input signal including an input node, a first output node N , and a path connecting the input and output nodes; a current switching circuit for applying a first current to the node N during a first mode of operation but not during a second mode; and a current source for applying a second current to the node N during both of the first and second modes. The value of the first current is determined such that the total current in the path is constant during the first and second modes. In an illustrative embodiment, the first mode is a track mode and the second mode is a hold mode.

High-performance track and hold circuit

An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) ( ) with a novel active offset method for comparators. The novel ADC architecture ( ) includes a first circuit ( ) for receiving an input signal; a second circuit ( ) for setting a predetermined number of thresholds using a predetermined number of preamplifiers ( ) with weighted unit current sources ( ) in each of the preamplifier outputs; and a third circuit ( ) for comparing the input to the thresholds. In the preferred embodiment, the ADC ( ) includes trimmable current sources ( ). The ADC ( ) of the present invention also includes an improved comparator circuit ( ). The novel comparator ( ) includes split load resistors, pairs R (active mode) and R and pairs R (active mode) and R , to increase the acquisition time and reduce the regeneration time constant, emitter follower buffers Q and Q on the latch pair transistors Q and Q to reduce the capacitive loading on the regeneration node, and cascode transistors Q and Q coupled to the load resistors to eliminate the output loading effects from the regeneration node. In the preferred embodiment, the invention also includes a novel DDS/DAC architecture ( ) with digitally trimmed unary currents and a novel sine lookup and decoder design which overcomes the conventional dynamic range limitations at high conversion rates.

Growing community of inventors

Carlsbad, CA, United States of America

Don C Devendorf