Cray Research, Inc.

Ati International Srl

Supercomputer Systems Limited Partnership

Advanced Micro Devices Corporation

Other

Silicon Graphics, Incorporated

Don A Van Dyke

George A Spix

Douglas R Beard

Andrew E Phelps

Alexander A Silbey

Frederick J Simmons

Richard G Blewett

Michael A Woodmansee

Jeffrey A Lohman

Korbin S Van Dyke

Stephen C Purcell

James C Rasbold

Paul W Campbell

Ali Alasti

Jon A Masamitsu

Robert E Strout, Ii

David M Cox

David A Seberger

Kelly T O'Hair

Timothy J Cramer

Linda J O'Gara

Ashok Chandramouli

Richard E Hessel

Steve S Chen

Diane M Wengelski

Gregory G Gaertner

Keith J Thompson

Jeremiah D Burke

Steven G Oslon

Mark D Johnson

David M Barkai

Stuart W Hawkinson

Giacomo G Brussino

Niteen Aravind Patkar

Shalesh Thusoo

Govind V Malalur

A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Method and apparatus for dynamic allocation of processing resources

A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

A structure and associated method to implement encryption/decryption under the Data Encryption Standard (DES). Several additional instructions are included in the instruction set of a general purpose microprocessor to operate in conjunction with hardware included in a data path of the general purpose microprocessor. The additional instructions perform a portion of the DES algorithm, in particular, a portion of a DES round. The state information used at each step of the encryption portion of the DES algorithm is provided in various general purpose registers of the general purpose microprocessor. In one embodiment, all sixteen subkeys are selected prior to the DES step in the general processor after a DES key is known. In another embodiment, each subkey is selected during the round it is used. In yet another embodiment, each subkey is selected during the round it is used, as part of an additional instruction executed by the general purpose microprocessor.

Encryption/decryption instruction set enhancement

A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set. The CISC instruction set provides accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set.

Computer for execution of RISC and CISC instruction sets

A method and apparatus for processing program instructions, utilizes native fixed length instructions that include at least one flag modification enable bit. The flag modification enable bit is typically sent with the operation code and other information in the native instruction and is set to allow updating of one or more flags, such as stored in flag registers, associated with non-native instructions, such as variable length instructions. In addition, a flag modification enable bit may be set to preserve flag bit setting for variable length instructions that are emulated using the fixed length native instructions, to prevent overwriting of flag settings during emulation of variable length instructions.

Multi-instruction set flag preservation apparatus and method

An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

Method of manufacture and apparatus of an integrated computing system

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes

A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include scalar registers, and the vector resources include vector registers. Decoding means decodes each of a number of address fields. Each field represents a register address to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below a selected moveable address value within a range of addresses encompassed by the address field.

Partitioned addressing apparatus for vector/scalar registers

An improved high performance hardwired supercomputer data processing apparatus includes instruction means adpated to issue one and two parcel instructions. Instruction fetch means provides an instruction stream of two parcel items in sequence. Instruction decode means is responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction or two one parcel instructions, for issuing each two parcel instruction for execution during the one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during the one clock cycle and the next succeeding clock cycle.

Data processing system for processing one and two parcel instructions

A delayed branch mechanism maintains the flow of an instruction pipeline in a scalar/vector processor having an instruction cache and including instruction fetch means, a program counter, and instruction decode/issue means coupled to the instruction cache by means of the instruction pipeline. Conditional branch instructions are rated as likely conditional branch instructions or unlikely conditional branch instructions based on a probability that their branch conditions will be met. A number of pipeline clock periods required for testing the branch conditions are determined. The likely conditional branch instructions are issued and executed including transferring a branch-to-address to the program counter during the number of pipeline clock periods irrespective of a successful meeting of the branch conditions. A number of useful instructions sufficient to issue within the number of pipeline clock periods are placed into the instruction stream following the likely conditional branch instructions. A conditional branch instruction is canceled and returned to an instruction which would have followed the conditional branch instruction if the branch is not taken. No gap occurs in the instruction stream if the corresponding branch is successfully taken.

Method of processing conditional branch instructions in scalar/vector

The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.

Vector/scalar processor with simultaneous processing and instruction

A vector processing system includes a main memory, vector registers, vector resources for accessing memory to transfer vector data between main memory and the vector registers and to perform operations on the vector data. Data words stored in non-consecutive address locations of a segment of main memory are accessed for processing. Offset address values of a number of the data words are stored in consecutive elements of a first vector register. A vector gather instruction is executed which adds each offset address value to a base address value to calculate main memory addresses representing main memory storage locations of the data words, retrieves the data words from the main memory, and stores the data words in consecutive elements of a second vector register in an order corresponding to that in which the offset address values are stored in the first vector register. A second vector instruction is chained to the gather instruction for performing an operation upon the retrieved data words and storing the results in a third vector register. A vector scatter instruction is chained to the second vector instruction to return the results to the main memory.

Method and apparatus for chaining vector instructions

A sequence of conditional vector IF statements is processed by employing a mask register and a condition register. Each conditional vector IF statement is typically performed on two vector registers, each having vector elements. A first conditional vector IF statement in the sequence is processed for those vector elements corresponding to set bits in the mask register. Bits are set in the condition register to reflect those vector elements which correspond to the set bits in the mask register for which the conditional vector IF statement is satisfied. The contents of the condition register are then moved into the mask register. A next conditional vector IF statement in the sequence is then processed for those vector elements corresponding to the new set bits in the mask register. Bits are then set in the condition register to reflect those vector elements which correspond to the new set bits in the mask register for which the conditional vector IF statement is satisfied.

Method of processing a sequence of conditional vector IF statements

A vector processor includes functional unit paths, each having an input and an output, and with at least one functional unit path including a plurality of pipelined functional elements coupled to the respective path input and output in parallel. The functional elements have different pipeline lengths to complete processing of operands applied to the path input. Program instruction initiation means responds to a first instruction to initiate processing of first operand data in a first of the functional elements, and responds to a second instruction to initiate the processing of second operand data in a second of the functional elements dependent upon completion of the first instruction but only if the second functional element has a pipeline length equal to or greater than the pipeline length of the first functional element.

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Pleasanton, CA, United States of America

Don A Van Dyke