International Business Machines Corporation

Dominique P Bonneau

Vincent Vallet

Philippe Hauviller

Seiki Ogura

Pascal R Tannhof

Pierre B Mollier

Patrick Mone

Myriam Combes

Anthony J Dally

Disclosed herein is an improved serializer/deserializer (SERDES) circuit () having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (). To that end, a delay perturbation is added to the serial data stream at the serializer () output, typically using a variable delay (DEL) line (). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic () coupled to the DEL line and the deserializer circuit () analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Characterizing jitter sensitivity of a serializer/deserializer circuit

Serializer/deserializer circuit for jitter sensitivity characterization

A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Built-in self test system and method for high speed clock and data recovery circuit

The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are operable to count to a first value at the VCO frequency rate and to provide a first ending signal when the first value is reached. Second counting means are operable to count to a second value at the reference frequency rate and to provide a second ending signal when the second value is reached. The second counting means are also operable to provide a reference count value when the first value is reached by the first counting means. A state machine is responsive to the first and second counting means for selecting a VCO frequency range among the plurality of VCO frequency ranges such that the VCO free-running frequency obtained through the selected range gives the closest value to the reference frequency. The state machine comprises means for decrementing the reference count value provided by the second counting means and also means for comparing the decrementation duration to the counting duration of the second counting means. The selection of the best VCO frequency range is based on this comparison.

Apparatus and method for setting VCO free-running frequency

A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

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La Rochelle, France

Dominique P Bonneau