International Business Machines Corporation

Dominique M Omet

Sylvain Leforestier

Seiki Ogura

Pascal R Tannhof

Bertrand Gabillard

Pierre B Mollier

Gerard Boudon

Philippe Girard

Bernard A Denis

Herve L Beranger

Jean-Luc Peter

Franck Wallart

Claude Marzin

A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one.

Redundant read bus for correcting defective columns in a cache memory

There is described a double stage sense amplifier (4) in bipolar technology achieving very high speed operation without saturation or connection problems. For each memory cell column of the computer member system (1), a first stage or column sense stage (4.1) amplifies the differential input signal (V) produced on the pair of bit lines (BLL, BLR) according to the information read from one CMOS memory cell of the memory cell array (3.1) to provide a first differential output signal (V1) available at output terminals (10.1, 10.2). The output terminals of all the first stage (4.1 to 4.n) are connected to a first-data out bus comprised of the data lines (DLC1, DLT1). A second stage or final stage (4') amplifies the first differential output signal developed on the data lines to provide a second differential output signal (V2) at output terminals (17.1, 17.2). The second stage of the common base amplifier type is comprised of two transistors (T9, T10). The base electrodes of these transistors are connected to a reference voltage generator (13) which supplies a reference voltage VREF such as VREF=VH-1.5 VBE. This special value greatly helps both first and second stages not to saturate and in addition, minimizes the sensibility of the sense amplifier to the connection of additional memory cell columns on the data lines (DLC1, DLT1). Both stages are provided with various antisaturation circuits (9, 11.1; 11.2, 16.1, 16.2) which cooperate with the reference voltage generator to keep any transistor far from saturation.

Double stage bipolar sense amplifier for BICMOS SRAMS with a common base

The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.

Complementary emitter follower drivers

A two stage address decoder circuit (AD) for 1/64 decode operation is disclosed which operates at high speed with low power consumption. Briefly stated, the circuit includes a first stage comprised of two predecoder circuits operable to develop predecoded output signals in response to input address signals and corresponding inverted address signals. Each predecoder circuit consists of a lower power high speed Differential Cascode Current Switch tree with its associated current source. The second or final decode stage is comprised of a plurality of final decoding circuits. Each final circuit consisting of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one pair of the predecoded output signals. Final decoder circuits provide final decoded output signals which drive the word lines of a memory cell array. The switched current source is triggered by a control signal supplied by a clock generator (CG) so that the final decode circuits consume power only when the control signal is active.

Two stage address decoder circuit for semiconductor memories

Memory comprising a matrix of conventional Harper pnp cells and peripheral circuits which allows it to be used either as a random access memory or as an associative memory. In addition to the read/write circuits which are inhibited in search mode, it comprises search mode control circuits 7-1 to 7-m to provide the memory cells with a search argument DI-1 to DI-m and search circuits 11-1 to 11-n connected to the word lines for detecting the match or mismatch conditions. A search restore circuit 15 common to all word lines WL is used to restore the work lines to a quiescent voltage once the search operation is completed. Circuits 7 and 11 are inhibited in read/write mode.

Memory using conventional cells to perform a ram or an associative

A power-supply system for use in a monolithic memory characterized in that the power dissipation of the memory is reduced. Each word line is connected to a current switch circuit comprised of a first transistor the collector of which is connected to a voltage V1, its base being connected to the output of the address decoder, a second transistor the collector of which is connected to a voltage V2. V3 being the second voltage impressed on the memory cells (where .vertline.V2.vertline. is larger in magnitude than .vertline.V1.vertline. and .vertline.V3.vertline. is larger in magnitude than .vertline.V2.vertline.). The emitters are connected to each other and to the corresponding word line. According to the state of the decoder output, the first or the second transistor is conducting, whereby the selected cells are subjected to a voltage having a magnitude of .vertline.V3-V1.vertline. and the non-selected cells are subjected to a voltage having a magnitude of .vertline.V3-V2.vertline..

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Corbeil, France

Dominique M Omet