Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Dominique Delbecq

Birama Goumballa

Cristian Pavao-Moreira

Cristian Pavao Moreira

Gilles Montoriol

Jean-Stephane Vigier

Didier Salle

Olivier Vincent Doare

Pierre Pascal Savary

Julien Orlando

Olivier Vincent Doaré

Ralf Reuter

James A Stephens

Gustavo Adolfo Guarin Aristizabal

Laurent Gauthier

Andres Barrilado Gonzalez

Arnaud Sion

Paul Wielage

Robert Gach

Matthis Bouchayer

Marcel Welpot

Francesco d'Esposito

Jean-Stéphane Vigier

Cristian Pavao-Moriera

Fares Jaoude

Andres Barrilado-Gonzalez

Daniel M Perrine

Ayoub Rifai

A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.

System and method of digital to analog conversion using dynamic element matching

The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver () having a normal mode of transmitter operation and a self-test mode of operation, the transceiver () comprising: a digital controller () configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter () configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter () configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load () connected to receive the analogue signal from the digital to analogue converter () and to provide an analogue output; a resistor network () connected across an output of the dummy load (); a testing module () configured to measure the analogue output of the dummy load (); and a controller module () configured to control operation of the dummy load (), testing module () and digital controller () during the self-test mode of operation by: enabling the dummy load (); operating the digital controller () to provide a range of digital control signals to the digital to analogue converter (); and operate the testing module () to measure the analogue output of the dummy load () to determine a measure of linearity of the digital to analogue converter ().

Radar transceiver

A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.

Phase rotator control apparatus and method therefor

A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.

Phase rotator calibration apparatus and method therefor

A communication unit () is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit () configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (); and transmit the modulated master-slave clock signal () to the at least one slave device. The at least one slave device comprises a demodulator circuit () configured to: receive and demodulate the modulated master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit and method for clock distribution and synchronization

A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Chirp linearity detector for radar

A radar device () is described that includes at least one transceiver () configured to support frequency modulated continuous wave (FMCW); a digital controller (); and a temperature sensor system comprising a plurality of temperature sensors () coupled to various circuits () in the at least one transceiver (). The digital controller () of the radar device () is configured to monitor a temperature of the various circuits () by polling temperature values of the plurality of temperature sensors ().

Temperature sensor system, radar device and method

A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator. The controller comprises a cyclic-redundancy-check calculator and is configured to determine an expected cyclic-redundancy-check result from expected values for each of the set of registers, to read the cyclic-redundancy-check result for each of the set of registers determined by the cyclic-redundancy-check generator, and to compare the generated cyclic-redundancy-check result with the calculated cyclic-redundancy-check result and wherein a difference between the generated cyclic-redundancy-check result and the calculated cyclic-redundancy-check result is indicative of an error condition.

Register error detection system

A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.

Charge pump driver circuit

The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. The saturation detector is configured to detect saturation events in the radar receiver, and the reset mechanism is configured to reset at least one filter unit in the radar receiver in response to detected saturation events. As such, the embodiments can facilitate improved radar sensitivity by reducing the effects of saturation events in the radar receiver.

Radar system and method with saturation detection and reset

An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.

Integrated circuit for saturation detection, wireless device and method of detecting saturation

A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift.

Radar device utilizing phase shift

A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value &#x3b8;, receive a second phase value &#x3b8;, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value &#x3b8;, and compute a second digital phase shift control value based on the received second phase value &#x3b8;. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.

Method and apparatus for generating phase shift control signals

An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

Integrated circuit, radar device and method of calibrating a receiver

A receiver unit comprising a mixer, a test signal unit, a multiplexer unit, an amplifier unit, a signal strength unit, and a digital control unit is described. The mixer may be arranged to downconvert a received radio-frequency signal to an intermediate frequency, thereby generating a reception signal having the intermediate frequency. The multiplexer unit may be connected to the mixer and to the test signal unit and arranged to select, among the reception signal and a test signal, a multiplexer output signal in dependence on an operating signal. The amplifier unit may be connected to the multiplexer unit and arranged to amplify the multiplexer output signal, thereby generating an amplified signal. The signal strength unit may be connected to the amplifier unit and arranged to generate a signal strength indicator indicative of a signal strength of the amplified signal. The control unit may be connected to the signal strength unit and arranged to generate the operating signal in accordance with an operating cycle, the operating cycle comprising one or more test phases and a reception phase. The test signal unit may be connected to the control unit and arranged to generate the test signal in dependence on the operating signal, the test signal having the intermediate frequency. The control unit may be further arranged to: gather, in each of the test phases, a test value of the signal strength indicator, thus gathering one or more test values; determine a numerical transformation on the basis of the one or more test values; gather, in the reception phase, a reception value of the signal strength indicator; and compute a corrected signal strength value by applying the transformation to the reception value.

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Fonsorbes, France

Dominique Delbecq