International Business Machines Corporation

Dominick Anthony Zumbo

Charles Louis Haymes

Hanafy E Meleis

Gary Scott Delp

Paul S Chang

David Israel Seidman

Ahmed N Tantawy

Rafael M Montalvo

Barry C Goldstein

Asser Nasreldin Tantawi

Mon-Song Chen

Richard Allan Auerbach

Hanafy El Sayed Meleis

Alternate methods, devices and systems are presented for providing service providers and/or end users of mobile stations to monitor and/or report regions with high error rates and/or dead zones. A protocol is provided such as to yield the error occurrence, error rate and/or the address of the end user. In some embodiments it also contains location information and time of day information. This information may be collected from the G.P.S., and/or all or a portion of users when there is a significant transmission difficulty and/or an abundance of errors. The collected data forms a database which is analyzed to generate coverage maps. This may include the dynamic aspects of the mobile network. In another aspect of this invention, each mobile station periodically compares its current location with the data base. The results of this comparison enables the mobile unit to anticipate connection problems. In still another aspect of the invention, the comparison is performed by the service provider which notifies the end user.

Error correlation for wireless networks

A method and apparatus creates a virtual high bandwidth, bi-directional, communications link utilizing low and high bandwidth uni-directional links in opposite directions. The directions of the two uni-directional communications links can be dynamically reversed in response to changing traffic needs.

Method and apparatus for creating virtual high bandwidth data channels

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. The generic adapter manager prepares future response to anticipated requests for communications services which are functions of the current requests for communication services, such as preparing a response for an anticipated request for a next buffer by a current request for a receipt of data. The generic adapter manager stores the future responses at specified addresses in memory which can be read by a requester. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

Generic high bandwidth adapter providing data communications between

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

Generic high bandwidth adapter having data packet memory configured in

An architecture for a low-end, high-performance switch subsystem allows the connection of a multitude of requests per link. The switch subsystem operates a cross-bar switch under the control of a controller, such as a personal computer, to connect selected ones of a plurality of input links to selected ones of a plurality of output links. A data structure for the switch subsystem is mapped to the memory of the controller. The switch subsystem comprises three switch servers, a request server, a connect server, and an acknowledge server, which perform in a pipelined fashion. An interface protocol for the switching subsystem may be adapted to various applications and allows a connect request to be either queued in the switch subsystem until the requested output link in available or the requestor is notified immediately if the requested output link is not available, so that alternate actions can be taken.

Low-end high-performance switch subsystem architecture

A communication system provides high speed transmission of data over a link, such as a fiber optic link, between a first terminal and a second terminal. The architecture and protocol permits the use of dedicated hardware such as state machines constructed of programmable array logic units, to synchronize the transmission and reception of data packets and the retransmission of designated ones of these packets in the event of a faulty transmission. Packets to be transmitted and received are stored in an array of frames in sub-windows of a memory storage window in each of the termianls, the frame number being equal to the sequence number of the data packet. By embedding sequence and status bits in each packet within control words and bits appended to each packet, the state machine in each terminal can readily track the progress of each packet so as to request acknowledgement of error-free receipt, to send an acknowledgement, to request a retransmission of a packet designated by its serial number and to distinguish a retransmitted packet from an original packet transmitted with error.

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Carmel, NY, United States of America

Dominick Anthony Zumbo