Arm Limited

Dominic William Brown

Christopher Vincent Severino

Ashley John Crawford

Seow Chuan Lim

Gergely Kiss

Csaba Kelemen

Andrew Brookfield Swaine

Tessil Thomas

Paul Gilbert Meyer

Mark David Werkheiser

Richard Andrew Paterson

Peter Czakó

Patrick Michael Overs

A data processing apparatus includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus-2. The mapping parameters may be fixed or software programmable.

Power control circuitry for controlling power domains

A data processing system and method are provided for outputting from each of a plurality of monitoring units, for storage in storage circuitry, monitoring data indicative of a property of the data processing system, wherein at least one monitoring unit is provided within a power domain operable in a low power mode where the at least one monitoring unit is unable to output monitoring data. A system control processor is employed to read the monitoring data from the storage circuitry, and to perform system control operations in dependence on the monitoring data. In response to a notification that the power domain is to be placed into the low power mode, status data is output indicating that the at least one monitoring unit is disabled, and the status data is stored in the storage circuitry. Subsequently, the status data is provided to the system control processor in response to an attempt to read the monitoring data.

Data processing system and method for monitoring system properties

Aspects of the present disclosure relate to power bridge circuitry comprising a first interface configured to interface with a source power domain; a second interface configured to interface with a target power domain; transition circuitry to receive a transition indication that the power bridge circuitry is to transition to an idle state; communication circuitry to communicate messages between the interfaces; and message identification circuitry to identify messages communicated by the communication circuitry, the identification circuitry being configured to detect the communication of a given message directed to a target component connected to the second interface and indicating cessation of communication between the target component and a source component connected to the first interface. The transition circuitry is configured, responsive to receiving the transition indication and responsive to the message identification circuitry detecting communication of the given message, to initiate a transition of the power bridge circuitry to the idle state.

Methods and apparatus for interfacing between power domains

An integrated circuit and method are provided for managing power domains. The integrated circuit has first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state. Further, the additional power control circuitry is arranged to output a mode status signal that is then used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain. This ensures that, despite the power control circuitry losing knowledge of the current power state of the first power domain whilst it is in the power saving state, no unintended consequences occur when the second power domain subsequently exits the power saving state.

Technique for managing power domains in an integrated circuit

A data processing apparatus has a number of devices having a normal state and a quiescent state in which the device is ready for being placed in a power saving state. Each device provides at least one preference indication indicative of a preference to operate in the normal state or the quiescent state. A controller controls a common state transition process for transitioning each of the devicesbetween the normal state and the quiescent state based on the preference indication received from each device.

Controlling transitions of devices between normal state and quiescent state

An integrated circuit () has first and second domains (). The first domain has a power controller () to control the power state of at least one device () in the second domain based on power management signals exchanged on a power management channel () between the first and second domains A reset isolation bridge () is provided on the power management channel () between the first and second domains (). The bridge () has first and second interfaces () to exchange the power management signals with the first and second domains respectively. Isolating circuitry () is provided in the bridge () to respond to a reset indication () indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces () from each other.

Reset isolation bridge

A data processing system includes multiple powered domains which communicate using a bridge. The bridgeincludes first bridge circuitrywithin a first power domain and second bridge circuitrywithin a second power domain. The first bridge circuitryand the second bridge circuitryexchange intra-bridge power control signals which serve to control management of the communication channel through the bridgeto adopt a communication open state or a communication quiesced state independent of whether either side of the bridge is in a power-active state or a power-inactive state.

Power control of inter-domain transaction bridge

A data processing apparatus () has a number of devices () having a normal state and a quiescent state. Transition sequencing circuitry () controls a sequential state transition process for transitioning each of the devices () in turn between the normal state and the quiescent state. For each device, the transition sequencing circuitry () controls the transition based on at least one preference indication transmitted from that device () providing an indication of a preference to operating the normal state or the quiescent state.

A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.

Segregated power state control in a distributed cache system

An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is currently ready to receive the data item.

Interface apparatus and method

Various implementations described herein are directed to a method and apparatus for a low power interface combiner for controlling a cross domain component in a system of two or more power domain controls. The combiner may include a first state for requesting cross domain component quiescence when a first control requests quiescence and a second state for ensuring cross domain component quiescence before accepting the first control quiescence request. The combiner may include a third state for requesting cross domain component quiescence exit when a last control requests quiescence exit and other controls have exited or are exiting quiescence. The combiner may include a fourth state for ensuring cross domain component quiescence exit before accepting the last control quiescence exit request.

Combination of control interfaces for multiple communicating domains

There is provided a data processing device including an output port to transmit a request value to an interconnect arranged to implement a coherency protocol, to indicate a request to be subjected to the coherency protocol. An input port receives an acknowledgement value from the interconnect in response to the request value and coherency administration circuitry defines behavior rules for the data processing device in accordance with the coherency protocol and in dependence on the request value and the acknowledgement value. Storage circuitry administers data in accordance with the behavior rules. There is also provided an interconnect including an input port to receive a request value, issued by a data processing device having storage circuitry, to indicate a request for the data processing to be subjected to a coherency protocol. An output port transmits an acknowledgement value to the data processing device in response to the request value and coherency administration circuitry defines behavior rules for the interconnect in accordance with the coherency protocol and in dependence on the request value and the acknowledgement value.

Hardware based coherency between a data processing device and interconnect

An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. A system power controller controls operation of the component power control circuitry by setting a power mode lock condition therein. When the power mode lock condition is met the component power control circuitry cannot change the selected power mode of the component. Power control over the component is thus partially delegated from the system power controller to the component power control circuitry.

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Ely, United Kingdom

Dominic William Brown