Agere Systems Inc.

Dominic W Yip

Tomasz Prokop

Gongyu Zhou

Uwe Sontowski

Rami Banna

Adriel P Kind

A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

Delay compensation in equalizer-based receiver

In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating.

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Carlingford, Australia

Dominic W Yip