Hewlett-Packard Company

Hewlett-Packard Development Company, L.p.

Dominic Paul McCarthy

Andrea Olgiati

Stuart Victor Quick

Stephen Morley

Peter Joseph Bramhall

Kevin Lloyd-Jones

A computer system comprises a first processorand a second processorfor use as a coprocessor to the first processor. The system has a main memory. The system also has a decoupling elementsuch that instructions are passed to the second processorfrom the first processorthrough the decoupling element. This has the effects that the second processorconsumes instructions derived from the first processorthrough the decoupling element, and that the second processorreceives data from and writes data to the memory. The processing of instructions by the second processorcan thus be decoupled from the operation of the first processor This is particularly effective for processing of a computationally intensive task (such as a media computation) on an architecture with a general purpose first processor, using a second processoradapted for the computationally intensive task. This can effectively be combined with use of a buffer memoryadapted to exchange data particularly rapidly with the memoryin response to memory instructions, together with a further decoupling elementto decouple the buffer memoryfrom the first processor

Computer architecture containing processor and decoupled coprocessor

In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions, a burst controller for executing the burst instructions, a burst instructions element for providing burst instructions in a sequence for execution by the burst controller, and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute. Burst instructions are provided by the first processor to the burst instructions element and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the data buffer in accordance with burst instructions executed by the burst controller.

Memory and instructions in computer architecture containing processor and coprocessor

A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of '1's and '0's, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the &lsquo;1&rsquo;s and &lsquo;0&rsquo;s are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.

Data balancing scheme in solid state storage devices

A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed. Each such burst instruction includes or is associated with a parameter defining a spacing between locations in the memory to be accessed in response to that burst instruction, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data elements between the memory, at locations spaced in accordance with the spacing parameter, and the data buffer in a single memory transaction. The system is particularly applicable for processing media which has high spatial locality and regularity, but low temporal locality, and enables high performance to be extracted from cheap memory.

Method of operating a computer system by identifying source code computational elements in main memory

A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed. Each such burst instruction includes or is associated with a parameter defining a spacing between locations in the memory to be accessed in response to that burst instruction, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data elements between the memory, at locations spaced in accordance with the spacing parameter, and the data buffer in a single memory transaction. The system is particularly applicable for processing media data which has high spatial locality and regularity, but low temporal locality, and enables high performance to be extracted from cheap memory.

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Mountain View, CA, United States of America

Dominic Paul McCarthy