Trw Limited

Northrop Grumman Systems Corporation

Trw Northrop

Dominic P Carrozza

Gregory S Caso

David A Wright

Vincent C Moretti

Reginald Jue

Stuart T Linsky

Dennis A Nivens

Michael S Munoz

The invention is a receiver and a method of receiving data having a preferred application in a satellite receiver in accordance with the invention includes a memory () including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal from a plurality channels (X, Y and Z) and outputs the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and a decoder (), responsive to the data groups, which decodes the data samples within the data groups and outputs decoded data samples.

Buffering and sequencing of soft decisions of multiple channels into a single shared biorthogonal decoder

A method and apparatus for closed-loop power threshold leveling for a satellite communication system. An aspect of the present invention includes a plurality of user earth terminals (UET), a satellite and a network control center (NCC). The NCC polls the UETs to obtain power profile information. When polled, the UELTs form power profile responses and send the responses back to the NCC. The NCC forms a power profile database and statistically analyzes the power profile information to determine an uplink power threshold adjustment. The NCC transmits the uplink power threshold adjustment to the satellite, which adjusts an on-board uplink power level threshold in response to the uplink power threshold adjustment. In systems using mutltiple coding levels, the NCC determines uplink power offset values corresponding to the individual coding levels. The NCC delivers the uplink power offset values to the UETs which update their local power offset values.

Method and apparatus for controlling a transmission power threshold of a satellite communication system

An apparatus ( ), and method, for calibrating gain in satellite uplink receiver electronics includes an uplink receiver, a measurement processor, and an attenuator ( ). The measurement processor receives the uplink signal from the uplink receiver and includes circuitry to sample ( ) the uplink signals during a blanking interval and outputs a gain calibration signal. The sampling circuitry ( ) may sample uplink signals periodically or responsive to extreme changes in conditions, and may sample the uplink signal multiple times during a blanking interval to output a multiple measurement sample. The measurement processor may include averaging circuitry ( ) to produce a sample average. The method and apparatus ( ) may both be used with TDMA systems.

Method of and apparatus for calibrating receive path gain

An initial entry processor ( ) for use in a processing satellite ( ) in a satellite based communications system ( ) is provided having a buffer ( ), a detection and timing circuit ( ) and an identity circuit ( ). The buffer ( ) stores an initial entry burst ( ) transmitted from at least one terrestrial terminal ( ) to the processing satellite ( ). The detection and timing circuit ( ) detects the initial entry burst ( ) and determines a time of arrival of the initial entry burst ( ) relative to an initial entry burst slot ( ). The identity circuit ( ) determines an identity of the terrestrial terminal ( ) that transmitted the initial entry burst ( ) such that the time of arrival is used by the identified terrestrial terminal ( ) during subsequent communications with the processing satellite ( ).

Onboard initial entry processor for facilitating a satellite communication

The present invention is a demodulator and a method of demodulating burst communications. A demodulator ( ) includes a phase angle source ( ), coupled to a current received burst communication, which provides a phase angle of the current received burst communication; a comparator ( ), coupled to the phase angle source and a source of an estimated phase angle, which provides an output signal representing an angular difference between a phase of the current received burst communication and the estimated phase angle; and a phase lock loop ( ), coupled to the output signal, which provides the estimated phase angle. The phase lock loop includes a Doppler accumulator ( ) which provides a Doppler output which provides compensation in the estimated phase angle for the Doppler effect produced by relative motion between the demodulator and a source of the burst communications.

Doppler learning phase lock loop for burst demodulator

The invention is a receiver and a method of receiving data having a preferred application in a satellite. A receiver in accordance with the invention includes at least one memory ( ), each memory including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal and outputs the stored data samples from a plurality of channels in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and an outer decoder ( ), responsive to data blocks with each data block containing at least one data group, which decodes the data blocks and outputs decoded data blocks.

Serial to parallel conversion of data to facilitate sharing a single buffer among multiple channels

An uplink demodulator system ( ) for use in a processing satellite ( ) in a satellite based communications system ( ) is provided with a first multiplexer ( ), a second multiplexer ( ), a multichannel preamble processor ( ), and a multichannel phase tracker ( ). The first multiplexer ( ) is operable to receive channelized data from a plurality of channelization modes at a plurality of inputs and operable to route the channelized data to a first output. The multichannel preamble processor ( ) is operable to determine a phase estimate for each channel of the channelized data. The multichannel phase tracker ( ) is operable to receive the phase estimates from the multichannel preamble processor ( ) and operable to track a phase for each channel of said channelized data to phase align each channel of said channelized data to corresponding uplink signals. The second multiplexer ( ) is operable to multiplex and route heavy encoded channelized data and light encoded channelized data to a second output where the multiplex channelized data is phase aligned with the corresponding uplink signals.

Uplink demodulator scheme for a processing satellite

A synchronization burst processor ( ) used in a processing satellite ( ) in a satellite based communications system ( ) is provided with a sync burst memory ( ), a first double correlator ( ), a second double correlator ( ) and a modulus module ( ). The sync burst memory ( ) stores at least one sync burst ( ) transmitted from a terrestrial terminal ( ) to the processing satellite ( ) where the sync burst ( ) is formed from a quadrature pair sample set &lcub;p, q&rcub;. The first double correlator ( ) performs an early correlation and a late correlation of the p samples relative to a sync burst slot ( ) to generate an early correlation Pe and a late correlation Pl. The second double correlator ( ) performs an early correlation and a late correlation of the q samples relative to the sync burst slot ( ) to generate an early correlation Qe and a late correlation Ql. The modulus module ( ) determines an early modulus Re and a late modulus Rl from the early correlations Pe and Qe and from the late correlations Pl and Ql. The early modulus Re and the late modulus Rl are used to determine if the sync burst ( ) is present in the sync burst slot ( ) and if the sync burst ( ) is early or late relative to the sync burst slot ( ).

Synchronization burst processor for a processing satellite

The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter ( ); a demultiplexer ( ), coupled to the analog to digital converter, a window presum ( ) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a cyclic shift ( &prime;), coupled to I output groups of data words.

Efficient digital channelizer system and method of operation thereof

An improved digital decision directed phase locked loop (DD-PLL) for use with short block codes using phase shifting keying (PSK) modulation. The improvement involves a conventional digital phase lock loop which is modified to base its loop corrections on the results obtained by decoding the short block code rather than on a symbol by symbol basis as is customary in conventional DD-PLLs. The improved method of loop corrections involves retaining the symbol data pending the decoder's decision, derotating the retained data in accordance with the decoded result, and integrating the derotated data to form a composite estimator upon which to base the loop correction. In its preferred embodiment, the invention uses an (8, 4) biorthogonal code with quatenary PSK.

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Redondo Beach, CA, United States of America

Dominic P Carrozza