International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Advanced Micro Device, Inc.

Dominic Joseph Schepis

Alexander Reznicek

Kangguo Cheng

Ali Khakifirooz

Devendra K Sadana

Pouya Hashemi

Ghavam G Shahidi

Junedong Lee

Judson Robert Holt

Pranita Kerber

Qiqing Christine Ouyang

Effendi Leobandung

Joel Pereira De Souza

Atul Champaklal Ajmera

Stephen W Bedell

Krishna Seshan

Ashima B Chakravarti

Michael Patrick Chudzik

Abhishek Dube

Oh-Jung Kwon

Ronald Jay Bolam

John S Lechaton

Bruce Bennett Doris

Robert J Gauthier, Jr

Steven H Voldman

Dureseti Chidambarrao

Raschid Jose Bezama

Paul Christian Parries

Huajie Chen

Fariborz Assaderaghi

Michael D Steigerwalt

Keith E Fogel

Shogo Mochizuki

Thomas W Dyer

Henry K Utomo

Werner A Rausch

Klaus D Beyer

Huilong Zhu

Jack Allan Mandelman

Veeraraghavan S Basker

William R Tonti

Andres Bryant

Kern Rim

Renee Tong Mo

Vamsi Krishna Paruchuri

Hussein Ibrahim Hanafi

K Paul Muller

Leathen Shi

Shahab Siddiqui

Jerome Brett Lasky

Paul David Agnello

Charan V Surisetty

Diane Catherine Boyd

Erin C Jones

Shashi D Malaviya

Kris V Srikrishnan

Jinghong Li

Min Dai

Yue Ke

Linda R Black

Victor Ku

Brian W Messenger

William Hsioh-Lien Ma

Jeffrey P Gambino

Louis L Hsu

Rajiv V Joshi

Jeffrey W Sleight

Oleg Gluschenkov

Charles W Koburger, Iii

Zhijiong Luo

Haizhou Yin

Reinaldo Ariel Vega

Sanjay C Mehta

Thomas N Adam

Anthony I Chou

Dae-Gyu Park

Michael John Hargrove

James Gardner Ryan

Rishikesh Krishnan

Joseph F Shepard

Zhibin Ren

Jun Yuan

Michael D Armacost

Charan V V S Surisetty

Darsen D Lu

Seshadri Subbanna

Kenneth John Giewont

Keith Howard Tabakman

Timothy James McArdle

Claude Ortolland

Matthew J Sendelbach

Victor J Silvestri

Mithkal M Smadi

Sameer Hemchand Jain

Eric Adler

Eric C Harley

Manu J Tejwani

William C Wille

Scott W Crowder

Tina Jane Wagner

Devices and methods of fabricating vertical nanowires on semiconductor devices. A doped silicon substrate, a first insulator over the doped silicon substrate, a gate conductor over the first insulator, and a second insulator over the gate conductor. Silicon nanowires extend from the top surface of the substrate through the first insulator, the gate conductor, and the second insulator. A first contact extends from the gate conductor through the second insulator, a second contact extends from the substrate through the first insulator, the gate conductor, and the second insulator layer, and an insulating spacer material is positioned between the second contact and the gate conductor.

Transistors and methods of forming transistors using vertical nanowires

Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Transistor structure with varied gate cross-sectional area

Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.

A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins.

Fin replacement in a field-effect transistor

A method of forming an SOI fin using a porous semiconductor. The method may include forming a stack of semiconductor layers on a substrate, the stack includes a second semiconductor layer on a first semiconductor layer in a layered region; forming fins in the second semiconductor layer by etching a trench through an exposed portion of the of the second semiconductor layer; converting the first semiconductor layer into a porous semiconductor layer using a porousification process; and converting the porous semiconductor layer into an oxide layer.

Low-cost SOI FinFET technology

A method of forming semiconductor fins is provided. Sacrificial fins are provided on a surface of substrate. A hard mask layer, formed around the sacrificial fins and the gaps therebetween, is made coplanar with a topmost surface of the sacrificial fins. A fin cut mask then covers a portion of the sacrificial fins and partly covers a sacrificial fin. Trenches are formed in the hard mask layer by removing sacrificial fins not covered by the fin cut mask and that portion of the sacrificial fin not partly covered by the fin cut mask. Spacers are formed on the sidewalls of the trenches and a plug is formed in the trench formed by removing that portion of the sacrificial fin not partly covered by the fin cut mask. Semiconductor fins are grown epitaxially in the trenches having the spacers from the exposed surface of the substrate upward.

Fin cut without residual fin defects

One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

Semiconductor structure having insulator pillars and semiconductor material on substrate

A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer.

Fin field-effect transistor having an oxide layer under one or more of the plurality of fins

The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.

Self-aligned nanotube structures

A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Low defect III-V semiconductor template on porous silicon

A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height and located on a pedestal portion of a first oxide structure. The structure further includes a second silicon fin of a second height and located on a pedestal portion of a second oxide structure. The first oxide structure and the second oxide structure are interconnected and the second oxide structure has a bottommost surface that is located beneath a bottommost surface of the first oxide structure. Further, the second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar with a topmost surface of the second silicon fin.

Local SOI fins with multiple heights

A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

FinFET having highly doped source and drain regions

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Wappingers Falls, NY, United States of America

Dominic Joseph Schepis