Arm Limited

U-blox Ag

Dominic Hugo Symes

Simon Andrew Ford

Ola Hugosson

Sven Ola Johannes Hugosson

Mladen Wilder

Daniel Kershaw

Daren Croxford

Andrew Christopher Rose

David James Seal

David Raymond Lutz

Christopher Neal Hinds

Luc Orion

Nicolas Chaussade

Simon Charles Watt

Erik Persson

Sharjeel Saeed

Lionel Belnet

Christopher Bentley Dornan

Tomas Fredrik Edso

Hedley James Francis

John Wakefield Brothers

David Hennah Mansell

Jayavarapu Srinivasa Rao

Jens Olson

Richard York

Stefan Johannes Frid

Stuart David Biles

Frederic Claude Marie Piry

Alastair David Reid

Edvard Fielding

Rune Holm

Sean Tristram Ellis

Guy Larri

Viacheslav Chesnokov

Stephane Eric Sebastien Brochier

Michal Bogusz

Donald Kenneth Felton

Martinus Cornelis Wezelenburg

Damian Piotr Modrzyk

Wilco Dijkstra

Tomas Fredrik Edsö

Fredrik Peter Stolt

Elliot Maurice Simon Rosemarine

Jared Smolens

Anders Berkeman

Michael Robert Nonweiler

Ozgur Ozkurt

Alex Kornienko

Brian Paul Starkey

Pontus Borg

Paul Matthew Carpenter

Jonas Christensson Cremon

Stephane Eric Sebastian Brochier

Philip Gregory Hall

Stephane Eric Brochier

Peter Mattias Hansson

Hui Chen

John Wakefield Brothers, Iii

Hedley James Frances

Ertunc Erdil

Chi-wen Cheng

Robert Norberg

Richard Edward Bruce

A processor comprising storage, execution circuitry and a handling unit configured to generate execution instructions to instruct the execution circuitry to execute a sub-operation to generate output data. The execution instructions comprise location data for prior data generated during execution of a prior sub-operation. The execution instructions instruct the execution circuitry to use the output data to update data stored within respective storage elements of a plurality of storage elements according to a predefined order, starting from an initial storage element determined based on the location data, so as to update the prior data using the output data. Further examples relate to a handling unit configured to generate execution instructions, comprising input location data, to instruct execution circuitry to re-read at least part of input data starting from an initial input storage element determined based on the input location data.

Re-accessing data

Methods and apparatus for performing a clipping operation comprised of a plurality of partial clip instructions based on a portion of a clip value. Wherein the partial clip instructions comprise decoding () a partial clip instruction using instruction decoding circuitry, and obtaining () at least a portion of input data associated with a register having a register size. In response to the decoded instruction the portion of the input data is clipped () based on the portion of the clip value; and a flag is set () indicating whether further clipping is required. The flag is set when an upper value of the portion of input data is equal to or exceeds the portion of the clip value.

Clipping operations using partial clip instructions

A processing unit is described that receives an instruction to perform a first operation on a first layer of a neural network, block dependency data, and an instruction to perform a second operation on a second layer of the neural network. The processing unit performs the first operation, which includes dividing the first layer into a plurality of input blocks, and operating on the input blocks to generate a plurality of output blocks. The processing unit then performs the second operation after the first operation has generated a set number of output blocks defined by the block dependency data.

Processing unit for performing operations of a neural network

Disclosed herein is a method of encoding an array of data elements comprising transforming the array from the spatial to the frequency domain, representing the frequency domain coefficients as a plurality of bit plane arrays, and encoding the set of frequency domain coefficients as a data packet having a fixed size by encoding the bit plane arrays in a bit plane sequence working from the bit plane array representing the most significant bit downwards until the data packet is full. Each bit plane array is encoded by recursively subdividing the bit plane array into respective sections and subsections down to the individual coefficients and including in the data packet, so long as there is available space, data indicating the locations of any (sub)sections in that bit plane array that for the first time in the bit plane sequence contain one or more coefficient(s) having a non-zero bit value.

Bit plane encoding of data arrays

A dot product array comprises dot product circuits each to process a respective pair of first and second input vectors to generate a respective dot product result. In a real number mode, each dot product result and vector element represents a respective real number. In a hypercomplex number mode, an input vector manipulation is applied to at least one of the first/second input vectors to be supplied to each dot product circuit, to cause the dot product array to generate hypercomplex dot product results each indicating a sum of hypercomplex products of corresponding pairs of hypercomplex numbers. In the hypercomplex number mode, respective subsets of elements of the first/second input vectors represent respective hypercomplex numbers, for which respective components are represented by different elements of the subset, and each hypercomplex dot product result comprises components represented by the dot product results generated by a corresponding group of at least two dot product circuits.

Dot product array

A processor to generate accumulated data comprising, for an operation cycle: performing an operation on a first bit range of a set of first input data to generate a set of operation data, which is accumulated with stored data within a first storage device. A lowest n bits of the accumulated data are accumulated with first further stored data within a first bit range of a second storage device, and are bit-shifted from the first storage device. Further accumulated data is generated, comprising, for an operation cycle: performing the operation on a second bit range of the set of first input data to generate a further set of operation data, which is accumulated with the stored data within the first storage device. A lowest m bits of the further accumulated data is accumulated with second further stored data within a second bit range of the second storage device.

Data accumulation

A data processing system including storage. The data processing system also includes at least one processor to generate output data using at least a portion of a first neural network layer and generate a key associated with at least the portion of the first neural network layer. The at least one processor is further operable to obtain the key from the storage and obtain a version of the output data for input into a second neural network layer. Using the key, the at least one processor is further operable to determine whether the version of the output data differs from the output data.

Data processing system and method

When performing anisotropic filtering when sampling a texture to provide an output sampled texture value for use when rendering an output in a graphics processing system, a number of positions for which to sample the texture along an anisotropy direction along which samples will be taken in the texture is determined by determining the square root of the coefficient F for an ellipse having the form Ax+Bxy+Cy=F corresponding to the projection of the sampling point for which the texture is being sampled onto the surface to which the texture is to be applied, and using the determined square root of the ellipse coefficient F to determine the number of positions for which samples should be taken along the anisotropy direction in the texture.

Graphics texture mapping

A method for performing neural network processing, and a corresponding data processing system. The data processing system is configured to define one or more tiles for use when reading a portion of an input feature map from memory or writing a portion of an output feature map to memory. The data processing system is also configured to provide information which allows positions falling within the defined one or more tiles to be mapped to memory locations to allow a processor to read data for an input feature map from memory or to write data for a portion of an output feature map to memory.

Neural network processing

When a producer processing unit, such as a video decoder, of a media processing system is producing a data output for use by a consumer processing unit, such as a display processor, the producer processing unit also generates metadata for the data output that it is producing and provides that metadata for use by the consumer processing unit. The consumer processing unit then uses the metadata provided by the producer processing unit when processing the data output to which the metadata relates.

Media processing systems

Herein described is a method of operating an accumulation process in a data processing apparatus. The accumulation process comprises a plurality of accumulations which output a respective plurality of accumulated values, each based on a stored value and a computed value generated by a data processing operation. The method comprises storing a first accumulated value, the first accumulated value being one of said plurality of accumulated values, into a first storage device comprising a plurality of single-bit storage elements; determining that a predetermined trigger has been satisfied with respect to the accumulation process; and in response to the determining, storing at least a portion of a second accumulated value, the second accumulated value being one of said plurality of accumulated values, into a second storage device.

Accumulating data values and storing in first and second storage devices

A method is described for operating on a frame of a video to generate a feature map of a neural network. The method determines if a block of the frame is an inter block or an intra block, and performs an inter block process in the event that the block is an inter block and/or an intra block process in the event that the block is an intra block. The inter block process determines a measure of differences between the block of the frame and a reference block of a reference frame of the video, and performs either a first process or a second process based on the measure to generate a segment of the feature map. The intra block process determines a measure of flatness of the block of the frame, and performs either a third process or a fourth process based on the measure to generate a segment of the feature map.

Operating on a video frame to generate a feature map of a neural network

A producer processing unit of a data processing system that is producing a stream of data for use by one or more consumer processing units of the data processing system maintains a record that is accessible to the consumer processing units of a position in the data stream for which it has written data to memory. The consumer processing units then control their reading of the data stream from the memory in accordance with the write position record maintained by the producer processing unit.

Data processing systems

An apparatus for encoding frames of a sequence of source frames of video image data to be encoded. The apparatus includes encoding circuitry configured to encode the source frames using reference frames. The apparatus also includes monitoring circuitry configured to, when the encoding circuitry is encoding a source frame using one or more reference frames, monitor the memory bandwidth being used when using the one or more reference frames when encoding the source frame. The apparatus further includes encoding circuitry that is operable to, in response to the monitored memory bandwidth being greater than a threshold, to control the encoding circuitry to encode a subsequent part of the source frame using a modified video encoding process to restrict the memory bandwidth usage when using one or more reference frames when encoding a subsequent part of a source frame.

Video data processing system

A method of operating a data processing system is disclosed for a data processing system that comprises a display and a display controller operable to provide to the display data in respect of output surfaces to be displayed. The method comprises, when an output surface is to be displayed, the display controller providing to the display data in respect of the output surface in the form of image data and image modification data, and the display using the image data and the image modification data when producing an output surface for display.

Providing output surface data to a display in data processing systems

Growing community of inventors

Cambridge, United Kingdom

Dominic Hugo Symes