Nvidia Corporation

Dominic Acocella

Henry Packard Moreton

Justin S Legakis

Robert W Gimby

Andrew D Bowen

Thomas H Kong

Mark R Goudy

David Conrad Tannenbaum

Christopher James Goodman

Andrew J Tao

Craig Michael Wittenbrink

Timothy J McDonald

Thomas Melvin Ogletree

Jeffrey B Moskal

Steven Gregory Foster, Jr

A method and system for remapping units that are disabled to active units in a 3-D graphics pipeline. Specifically, in one embodiment, a method remaps processing elements in a pipeline of a graphics pipeline unit. Graphical input data are received. Then the number of enabled processing elements are determined from a plurality of processing elements. Each of the enabled processing elements are virtually addressed above a translator to virtually process the graphical input data. Then, the virtual addresses of each of the enabled processing elements are mapped to physical addresses of the enabled processing elements at the translator. The graphical input data are physically processed at the physical addresses of the enabled processing elements. In addition, each of the enabled processing elements are physically addressed below the translator to further process the graphical input data.

Method and system for remapping processing elements in a pipeline of a graphics processing unit

Methods, apparatuses, and systems are presented for performing multiple concurrent accesses in a shared memory resource comprising storing a first group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the first group being stored in a data entry in a first bank; skipping at least one data entry in at least one bank after storing a last data element of the first group, to introduce an offset; following the offset, storing a second group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the second group being stored in a data entry in a second bank different from the first bank; and concurrently accessing the first data element of the first group from the first bank and the first data element of the second group from the second bank.

Concurrent access of data elements stored across multiple banks in a shared memory resource

An output buffer in a multi-threaded processor is managed to store a variable amount of output data. Parallel threads produce a variable amount of output data. A controller is configured to determine how much output buffer space is needed per thread and how many threads can execute in parallel, given the available space in the output buffer. The controller also determines where each thread writes to in the output buffer.

Configurable output buffer ganging for a parallel processor

Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.

System and method for delivering multiple data streams via multiple buses

A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache window can be a subset of the entire circular buffer. If contents within the cache window are identified as persistent data, the locations corresponding to the persistent data can be identified as permanent memory locations. The position of the cache within the circular buffer can be frozen based on the permanent memory locations. A write mask can be used to maintain the contents of the permanent memory locations, while the remainder of the cache is configured as a temporary circular buffer. Operation of the cache returns to the entire circular buffer once the contents of the permanent memory locations no longer need to be maintained.

Creating permanent storage on the fly within existing buffers

Method and apparatus for neighbor and edge indexing is described. A vertex is identified and assigned a reference. One-ring neighbor vertices of the vertex are identified. The reference is assigned to each of the one-ring neighbor vertices identified. An index to one of the one-ring neighbor vertices is assigned. The index is successively incremented to provide indices for each of the one-ring neighbor vertices remaining. Edge indexing follows as described above, with the vertex and its one-ring neighbors defining end points of edges. Additionally, offset indexing is described, and may be used for a consistent order of computation.

Neighbor and edge indexing

The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

Cull before attribute read

Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that improve utilization of storage buffers by overwriting data in them as soon as the data is no longer needed. An exemplary embodiment employs a counter to add each time a particular unit of data is needed by a circuit. The counter also subtracts each time the data is actually used by the circuit. When the counter reaches zero, upstream circuitry is checked to see if a command allowing the particular data to be overwritten has been issued. If it has, the command is not waited for, rather the data may be overwritten immediately. Embodiments of the present invention may also make use of one level of indirection to mask physical storage buffer locations from upstream circuitry. In this way, utilization can be improved.

Storage buffers with reference counters to improve utilization

Method and apparatus for generating a primitive extension defining a generalized primitive is described. The primitive extension defines the connectivity and vertices used to specify a collection of connected primitives, such as a strip-type or fan-type generalized primitive. A generalized primitive includes a number of vertices where some of the vertices are shared with neighboring primitives. The primitive extension includes an originating primitive, vertex data, and connectivity information. The primitive extension provides a general interface for describing a variety of connected primitives.

Primitive extension

A fixed function engine and method are described for processing a set of primitive commands. One embodiment of the fixed function engine includes a means for receiving one or more primitive commands, where each such primitive command includes information for processing vertex data using a user-developed program or subroutine. The fixed function engine also includes a means for determining a set of related primitive commands from the received primitive commands and a means for identifying a first primitive command to process from that set. In addition, the fixed function engine includes a means for transmitting a first program command, which is related to the first primitive command, to a processing engine for processing.

User programmable primitive engine

A programmable geometry engine is described. One embodiment of the programmable geometry engine includes a programmable primitive engine configured to receive primitive commands that include information for processing vertex data using user-developed programs or subroutines. The programmable primitive engine also is configured to transmit program commands that include program pointers and data pointers. In addition, the programmable geometry engine includes a processing engine configured to receive the program commands. The processing engine is further configured to retrieve the user-developed programs or subroutines using the program pointers and to retrieve vertex data using the data pointers. Also, the processing engine is configured to process the vertex data based on instructions included in the user-developed programs or subroutines to produce processed vertex data and to transmit results to the programmable primitive engine.

Growing community of inventors

Blainville, Canada

Dominic Acocella