Texas Instruments Corporation

Domingo G Garcia

Srinath Mathur Ramaswamy

Murtaza Ali

Mohamed Farouk Mansour

Michael Oliver Polley

Song Wu

Anand Ganesh Dabak

Baher S Haroun

Xiaolin Lu

Alan Gatherer

Gene A Frantz

Yuming Zhu

Charles Kasimer Sestok, Iv

Donald Phillip Shaver

Walter Y Chen

Alan Henry Leek

Douglas B Weiner

Dennis G Mannering

Sujeet Milind Patole

William C Timm

Terence J Riley

Paul E Schurr

Ryan Michael Brown

A transducer system with transducer and circuitry for applying a pulse train at a single frequency to excite the transducer. The transducer is operable to receive an echo waveform in response to the pulse train. The system also comprises circuitry for determining a time of flight as between a first reference time associated with the pulse train and a second reference time associated with the echo waveform.

Method and system for ultrasound time-of-flight measurement

A microcontroller-based system for measuring the impedance of a device under test (DUT), responsive to a square wave stimulus, includes parallel stimulus signal paths, selectable by a switch, that can correspond to different stimulus frequency ranges. At least one of the paths includes an off-chip PLL and integer divider circuit to modify the frequency of the stimulus. A discrete Fourier transform executed by a processor is used to determine the impedance of the DUT at the stimulus frequency. Multiple frequencies can be analyzed at the same time by using a summation circuit and/or by analyzing odd harmonics of the stimulus frequency.

Square-wave-based impedance analysis

An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to the demultiplexer. A first multiplexer is coupled to each of the sample buffers. A filter is coupled to the first multiplexer. A bypass delay circuit is coupled to the first multiplexer, and a second multiplexer is coupled to the filter and the bypass delay circuit.

Programmable wavelet tree

A timing recovery device for CAP/QAM modems includes an equalizer filter designed to monitor the movement of the filter coefficients within a memory buffer and to adjust the relative position of the filter coefficients within the memory buffer so that the coefficients remain substantially centered within the buffer.

Timing recovery device and method for telecommunications systems

A timing phase acquisition method and device for burst modems includes an receiver designed to initialize an equalizer filter by matching clock of the equalizer filter of the receiver with the phase of the received signal.

Timing phase acquisition method and device for telecommunications systems

A modem ( ) including receive circuitry ( ) implemented by way of a digital signal processor ( ) is disclosed. The receive circuitry ( ) operates according to a receive clock (CLK ) that is based upon the output of a free run oscillator ( ). An incoming frequency multiplexed signal (f(t)) is sampled by an analog-to-digital converter ( ) and demodulated by way of a Fast Fourier Transform function ( ). After such demodulation, a phase rotation function ( ) applies a phase shift to the demodulated signal corresponding to an estimated phase offset (&tgr;) between the receive clock (CLK ) and a pilot signal (P) transmitted by the transmitting modem; a finite impulse response filter function ( ) applies a digital filter to the demodulated signal to correct for phase error based upon an estimated frequency offset (&Dgr;). According to another disclosed embodiment, a pre-emphasis FIR filter function ( ) and a pre-emphasis phase rotation function ( ) are applied to an upstream singal, based upon the estimated phase offset (&eegr;) and frequency offset (&Dgr;).

Phase and frequency offset compensation in a telecommunications receiver

A system (10) is provided for performing binary correlation. The system (10) includes a plurality of reference bit registers (12-18). Each reference bit register (12-18) stores a reference bit of a reference sequence. A plurality of sequentially coupled data bit registers (20-26) can sequentially receive and store each data element of an input data stream. At least one programmable delay unit (28, 30) is coupled between sequential data bit registers (20-26). Each programmable delay unit (28, 30) delays at least one data element of the input data stream between the sequential data bit registers (20-26). A plurality of exclusive OR units (32-38) are each coupled to a corresponding reference bit register (12-18) and a corresponding data bit register (20-26). Each exclusive OR unit (32-38) performs an exclusive OR operation between a reference bit stored in the corresponding reference bit register (12-18) and a data element stored in the corresponding data bit register (20-26) in order to generate a resultant bit. A sum unit (40) is coupled to the exclusive OR units. The sum unit (40) sums the resultant bits generated by the exclusive OR units (32-38).

System and method for binary correlation

A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm. A first embodiment utilizes a high speed digital programmable filter (1532). Another embodiment utilizes a data buffer (1533) which is periodically filled with data filtered by a digital signal processor (DSP).

Multimode digital modem

Growing community of inventors

Plano, TX, United States of America

Domingo G Garcia