Stmicroelectronics S.r.l.

Domenico Repici

Angelo Magri′

Giuseppe Arena

Orazio Battiato

Fabrizio Marco Di Paola

Giuseppe Morale

Corrado Coccorese

Anna Borzi

In an MIS structure a field plate electrode is incorporated below a buried gate electrode by using an insulating oxide layer, which is formed concurrently with the gate dielectric layer. In order to obtain superior dynamic behavior and enhanced dielectric strength the oxidation behavior of the field plate electrode is modified, for instance by incorporating a desired high concentration of arsenic.

Method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates

According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.

Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture

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Rometta Marea, Italy

Domenico Repici