Stmicroelectronics S.r.l.

Stmicroelectronics Application Gmbh

Stmicroelectronics (alps) Sas

Domenico Massimo Porto

Giovanni Luca Torrisi

Sergio Lecce

Manuel Gaertner

Gianguido Rizzotto

Nicola Cesario

Paolo Amato

Marco Maria Branciforte

Ferdinando Taglialatela Scafati

Bianca Maria Vaglieco

Simona Silvia Merola

Vanni Poletto

Luigi Fortuna

Salvatore Abbisso

Riccardo Caponetto

Eusebio Di Cola

Christophe Roussel

Olga Diamante

Lucio Ticli

Ignazio Testoni

Antonio Calabro'

A method of compensating electromagnetic emissions of a device for use in a communication bus, the method including: transmitting a test signal over the communication bus; receiving, at the device, the test signal after propagation over the communication bus; performing frequency analysis processing of the test signal received to detect a set of harmonic components of the test signal received having an amplitude exceeding a certain threshold; storing respective values of frequency of harmonic components in the set of harmonic components having an amplitude exceeding the certain threshold; and generating and transmitting over the communication bus a set of compensation signals, each compensation signal in the set of compensation signals being a sinusoidal signal having a respective frequency equal to one of the frequencies stored, and being in anti-phase with respect to the harmonic component of the test signal received having the respective frequency.

Method of compensating electromagnetic emissions, corresponding circuit and device

An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

Method of operating H-bridge circuits and corresponding driver device

An embodiment circuit includes a plurality of heat-generating circuits, a heat-sensitive circuit exposed to heat generated during operation of the plurality of heat-generating circuit, and a temperature sensor disposed at a location between the heat-sensitive circuit and the plurality of heat-generating circuits, the temperature sensor being configured to generate an over-temperature signal as a function of temperature sensed at the location. The plurality of heat-generating circuits may be selectively deactivatable in an ordered sequence based on deactivation weights respectively assigned to the plurality of heat-generating circuits and in response to the over-temperature signal.

Circuit for thermal protection and method of operation thereof

A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

Thermal control process for a multijunction electronic power device and corresponding electronic power device

A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

Thermal control process for a multi-junction electronic power device and corresponding electronic power device

A driver for an electric load includes a power device having a control terminal and an output terminal for an output current, and a control module. The control module is configured to drive the power device in an auto-recovery mode by switching between activation and deactivation in the occurrence of an overcurrent condition, wherein the output current reaches a threshold current. The control module is also configured to evaluate a first time interval between a time wherein the overcurrent condition occurs, and a first time, and generate a limit signal when the time interval is equal to a time threshold. The power device is driven in a switching-off condition at least as a function of the limit signal.

Electric system comprising a load driving apparatus by auto-recovery mode, and method of operating the apparatus

QCA assemblies, in which basic cells are formed on the basis of graphene in order to provide a coupling field distribution in the form of an electrostatic field, a magnetic field, and the like which allows a unique association between field distribution and logic state. Moreover, the corresponding energy structure may be selected so as to allow operation of the QCA assemblies at ambient temperature. Hence, the signal processing capabilities of QCA assemblies may be obtained at significantly reduced complexity compared to conventional quantum-based QCA assemblies, which typically operate at very low temperatures.

Nanoscale QCA-based logic gates in graphene technology

A method for control of an internal combustion engine includes generating, with a microelectromechanical system (MEMS) accelerometer, an acceleration signal representing vibrations of the internal combustion engine. An engine crank angle signal is generated based on the acceleration signal. The engine crank angle signal is compared with a target value. The internal combustion engine is adjusted based upon the comparing.

Method and system for control of an internal combustion engine based on engine crank angle

A method of detecting during a combustion cycle a peak value of pressure in a cylinder of an internal combustion engine includes providing and installing on the engine body an accelerometer that generates an acceleration signal representing vibrations of the engine body. The acceleration signal is filtered by comparing the band-pass filtered replica of the acceleration signal to a threshold. When the threshold is surpassed, a pressure peak is detected and flagged.

Method and device for detecting peak values of pressure in a cylinder of an internal combustion engine

A hardware quantum gate for running quantum algorithms in a very fast manner exploits the fact that a large number of multiplications required by an entanglement operation of the quantum algorithm provides a null result since only one component per row of the entanglement matrix Uis not a null. The entanglement operation generates an entanglement vector by permuting pairs of opposite components of a linear superposition vector, depending on the value assumed by the function f. More specifically, if function f is null in correspondence to the vector identified by the first (leftmost) n qubits in common with the two n+1 qubit vectors, in which a pair of opposite components of the superposition vector is referred to, then the corresponding pair of components of the entanglement vector is equal to that of the superposition vector, otherwise it is the opposite.

Hardware quantum gate

A quantum gate for running a Grover's quantum algorithm using a binary function having a vector basis of n qubits is provided. The quantum gate includes a superposition subsystem, an entanglement subsystem and an interference subsystem. The interference subsystem performs an interference operation on components of entanglement vectors for generating components of output vectors. The interference subsystem performs the interference operation in a very fast manner by using an adder receiving as input signals representing even or odd components of an entanglement vector, and generating a sum signal representing a weighted sum with a scale factor of the even or odd components. The interference subsystem also includes an array of adders each input with a respective signal representative of an even or odd component of an entanglement vector and with the weighted sum signal, and generates a signal representative of an even or odd component of an output vector as a difference between the weighted sum signal and the signal representing an even or odd component of an entanglement vector.

Quantum gate for carrying out a grover's quantum algorithm and a relative method of performing the interference operation of a grover's quantum algorithm

A method of performing a Grover's or a Deutsch-Jozsa's quantum algorithm being input with a binary function defined on a space having a basis of vectors of n of qubits includes carrying out a superposition operation over input vectors for generating components of linear superposition vectors referred to a second basis of vectors of n+1 qubits. An entanglement operation is performed over components of the linear superposition vectors for generating components of numeric entanglement vectors. The method allows a non-negligible time savings because the entanglement operation does not multiply a superposition vector for an entanglement matrix, but generates components of an entanglement vector simply by copying or inverting respective components of the superposition vector depending on values of the binary function. An interference operation is performed over components of the numeric entanglement vectors for generating components of output vectors.

Method and relative quantum gate for running a Grover's or a Deutsch-Jozsa's quantum algorithm

A quantum gate performs the superposition operation of a Grover's or of a Deutsch-Jozsa's quantum algorithm in a very fast manner. This is done by performing all multiplications by using logic gates that immediately outputs the result. The superposition operation includes performing the Hadamard rotation over an input set of vectors for producing a set of rotated vectors, and calculating the tensor product of all the rotated vectors for outputting a linear superposition set of vectors. The tensor product of all the rotated vectors is carried out by the logic gates.

Method of performing the superposition operation of a Grover's or a Deutsch-Jozsa's quantum algorithm and a relative quantum gate

A circuit implementing a non-integer order dynamic system includes a neural network that receives at least one input signal and generates therefrom at least one output signal. The input and output signals are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network. A plurality of such circuits, implementing respective non-integer order controllers can be interconnected in an arrangement wherein any of the integral or differential blocks included in one of these circuits generates a signal which is fed to any of the integral or differential blocks of another circuit in the system.

Growing community of inventors

Catania, Italy

Domenico Massimo Porto