University of Florida Research Foundation Inc

University of Connecticut

Technische Universitaet Berlin

Domenic J Forte

Mark M Tehranipoor

Navid Asadizanjani

Haoting Shen

Damon Woodard

Ronald Wilson

Adib Nahiyan

Fatemeh Ganji

Nima Maghari

Kun Yang

Sreeja Chowdhury

Bicky Shakya

Qihang Shi

Swarup Bhunia

Navid Asadi-Zanjani

Farimah Farahmandi

Shahin Tajik

Fahim Rahman

Huanyu Wang

Ulbert Botero

Jungmin Park

Ujjwal Guin

Mohammad Sazadur Rahman

Jean-Pierre Seifert

Michael Levin

Sumaiya Shomaji

A method and system are directed to designing a low-dropout regulator (LDO) circuit and using the LDO circuit to detect recycled counterfeit integrated circuits. The LDO circuit includes, in part, a reference path circuit and a stressed path circuit. Each of the reference path circuit and the stressed path circuit is coupled to a control signal that can enable the corresponding path circuit for the LDO. LDO parameters can then be measured while the reference path circuit and the stressed path circuit is enabled respectively. The difference between the LDO parameters measured while the reference path circuit is enabled and while the stressed path circuit is enabled is used to determine if an integrated circuit comprising the LDO circuit is a recycled counterfeit.

LDO-based odometer to combat ic recycling

In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for setting up biometric access for a legitimate user to a design. In accordance with various embodiments, a biometric template is received originating from the user and is inputted to a first secure sketch generator configured to use first transformation parameters comprising a hash function to generate a protected biometric template by hashing the biometric template. The protected biometric template is inputted to a second secure sketch generator configured to use second transformation parameters comprising a physical unclonable function serving as a fingerprint of the design to generate an original obfuscation key from the protected biometric template. The original obfuscation key is then used to obfuscate the design to generate an original bitstream, wherein the first and second transformation parameters and the original bitstream are stored on the design.

Biometric locking methods and systems for internet of things and the connected person

Various embodiments of the present disclosure provide for accelerated segmentation for reverse engineering of integrated circuits. In one example, an embodiment provides for receiving an SEM image for an integrated circuit, performing filtering and binarization with respect to the SEM image, extracting information associated with filter sizes for the filtering, extracting signatures related to a distribution for background pixels and foreground pixels of the SEM image, extracting respective distance to mean signatures for the background pixels and the foreground pixels, and segmenting the SEM image based at least in part on the filter sizes and the respective distance to mean signatures to generate a segmented image for the integrated circuit.

Accelerated segmentation for reverse engineering of integrated circuits

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.

Hardness amplification of physical unclonable functions (PUFS)

Systems and methods are configured to generate a frequency map representing a density of objects found in regions of a sample that may be used in setting parameters for imaging the regions. Various embodiments involve binarizing the pixels for a raw image of the sample to transform the image into binary data. Run-length encoded components are identified from the data for dimensions of the raw image. Each component is a length of a sequence of adjacent pixels found in a dimension with the same value in the binary data. A projection of the image is then generated from projection values for the dimensions. Each projection value provides a measure of the density of objects present in a dimension with respect to the components identified for the dimension. This projection is used to identify a level of density for each region of the sample from which the frequency map is generated.

Automatic sharpness adjustment for imaging modalities

Embodiments of the present disclosure provide methods, systems, apparatus, and computer program products are for detecting whether a suspect component such as an integrated circuit (IC) or a system-on-chip (SoC) is recycled. Specifically, various embodiments involve processing power supply rejection ratio (PSRR) data obtained from a low drop-out regulator (LDO) used for the suspect component using a recycle detection machine learning model to generate a recycle prediction. In particular embodiments, the recycle detection machine learning model is developed based at least in part on degradation of PSRRs of LDOs. Accordingly, a determination is made as to whether the suspect component is recycled based on the recycle prediction. If so, then an indication that the suspect component is recycled is provided.

Detection of recycled integrated circuits and system-on-chips based on degradation of power supply rejection ratio

Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.

Comprehensive framework for protecting intellectual property in the semiconductor industry

A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.

Optical scrambler with nano-pyramids

Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.

CAD framework for power side-channel vulnerability assessment

Disclosed are various embodiments for detecting hardware Trojans through information flow security verification. A file comprising register transfer level (HDL) code for an intellectual property core is loaded from memory. An asset within the intellectual property core is identified. An integrity verification or confidentiality verification of the HDL code that represents the asset is performed. An integrity violation or confidentiality violation within the HDL code as a result of performance of the integrity verification or confidentiality violation on the HDL code that represents the asset is detected. A malicious control point or a malicious observation point linked to the asset is identified. Finally, a trigger circuit for a hardware Trojan is identified in response to identification of the malicious control point or malicious observation point.

Hardware trojan detection through information flow security verification

A histogram-based method for auto segmentation of integrated circuit structures is disclosed. The method includes an auto-segmentation process/algorithm, which works on the histogram of the SEM image and does not try to model the noise sources or the features. The auto-segmentation process/algorithm extracts the number of peaks in the histogram from low magnification SEM images or SEM images not necessarily having high quality images, significantly simplifies the traditionally lengthy and expensive IC reverse engineering efforts. Hence, the size of the image does not affect the final segmentation. The auto-segmentation process/algorithm performs the steps of: extract a first histogram from the first SEM image; identifying boundaries of the plurality of structural elements in the IC based at least in part on an output of the first histogram; and auto-segmenting the first SEM image into the plurality of structural elements.

Histogram-based method for auto segmentation of integrated circuit structures from SEM images

A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a &#x3c6;-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the &#x3c6;-bit protected Obfuscation Key generated by the LFSR, and output k&#x2514;&#x3c6;&#xd7;&#x3b1;&#x2518;-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

Protecting obfuscated circuits against attacks that utilize test infrastructures

Methods and apparatus are provided for automatically extracting standard cells to form a standard cell library using raw multi-layer images of an IC. Accordingly, various embodiments involve: extracting the raw contact layer image from the raw multi-layer images; binarizing the raw contact layer image to generate a binarized contact layer image identifying a plurality of contact rows and a plurality of contact columns; determining a plurality of Vlines based on a subset of the plurality of contact rows having a periodic nature; extracting a plurality of binarized contact layer image strips from the binarized contact layer image; encoding each binarized contact layer image strip using feature vectors and column distance values; applying a model rule set to each encoded binarized contact layer image strip for detecting cell boundaries; extracting the standard cells based on the cell boundaries; and storing the extracted cells to form a standard cell candidate library.

Method and apparatus for automatic extraction of standard cells to generate a standard cell candidate library

Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.

Prevention of front-side probing attacks

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Growing community of inventors

Gainesville, FL, United States of America

Domenic J Forte