Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Domagoj Siprak

Uwe Hodel

Harald Gossner

Marko Radosavljevic

Jong-Kae Fwu

Peter Baumgartner

Marc Tiebout

Han Wui Then

Sansaptak W Dasgupta

Markus Dominik Mueck

Bernhard Raaf

Jing Zhu

Nageen Himayat

Carlos Horacio Aldana

Shilpa Talwar

Hosein Nikopour

Yang-Seok Choi

Christian Drewes

Zhibin Yu

Dave A Cavalcanti

Stephan Henzler

Jerome Parron

Bertram Gunzelmann

Biljana Badic

Sabine Roessel

Harry G Skinner

Debabani Choudhury

Sudeep Manithara Vamanan

Ingolf Karls

Duncan Kitchin

Stephan Leuschner

Richard Geiger

Philipp Riess

Wolfgang Molzer

Giovanni Calabrese

Jonas Fritzin

Dario Sabella

Miltiadis Filippou

Paul-Werner Von Basse

Christian Peters

Thomas Scheiter

Daniel Kehrer

Michael Melzl

Shashanka Totadamane Ramappa

Reinhard Fischbach

Christopher Stobart

Heinz Opolka

Daniel Sira

Rajkumar Krishnaperumal

Nirlesh Kumar Koshta

Thorsten Sasse

Sundaravadanan Anantha Krishnan

Pierre Mayr

Johannes Kunze

Christopher Weyers

Rainer Grossmann

Andreas Gaymann

Thomas Rosteck

Reinhard G&ouml;llner

Klaus Hammer

Markus Witte

Justin Bierner

Steven A Bowers

Pradeep C Pangi

Bernd Schaller

A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Variable capacitance device with multiple two-dimensional electron gas (2DEG) layers

A central trajectory controller including a cell interface configured to establish signaling connections with one or more backhaul moving cells and to establish signaling connections with one or more outer moving cells, an input data repository configured to obtain input data related to a radio environment of the one or more outer moving cells and the one or more backhaul moving cells, and a trajectory processor configured to determine, based on the input data, first coarse trajectories for the one or more backhaul moving cells and second coarse trajectories for the one or more outer moving cells, the cell interface further configured to send the first coarse trajectories to the one or more backhaul moving cells and to send the second coarse trajectories to the one or more outer moving cells.

Methods and devices for wireless communications

An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.

High frequency capacitor with inductance cancellation

A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Group III-nitride Schottky diode

A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.

Group III-nitride silicon controlled rectifier

Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first plate. The finger to finger capacitor is in proximity to the first plate. The finger to finger capacitor includes a first plurality of finger elements and a second plurality of finger elements. The second plurality of finger elements is interleaved with the first plurality of finger elements. The first plurality of finger elements is electrically connected to the first plate and the second plurality of finger elements is electrically connected to the second plate. The second plurality of finger elements and the first plate form additional plate-to-plate capacitors.

Compound capacitor structures

A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Group III-nitride antenna diode

One embodiment described is an apparatus that includes an active device structured in a semiconductor body. The semiconductor body may include a gate terminal to receive a switched bias signal, and a bulk terminal to receive a forward body-bias signal. A first circuit portion may be coupled to the gate terminal to provide the switched bias signal, and a second circuit portion may be coupled to the bulk terminal to provide the forward body-bias signal.

Apparatus and method having reduced flicker noise

Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate. A trench isolation region is formed within the doped region. The doped region and the trench isolation region are part of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device. The trench isolation region or an interface between the trench isolation region and the doped region is configured to reduce low frequency noise in the LDMOS device.

Methods of forming low noise semiconductor devices

Semiconductor devices may be configured to reduce noise in the devices. For example, a semiconductor device may be configured or made with a first doped region within a semiconductor substrate to operate as an extended drain region, a trench isolation region, a second doped region between the first doped region and the trench isolation region, wherein the trench isolation region and the second doped region may be at least partially formed within the first doped region. Additionally, or alternatively, the second doped region may be within the first doped region and at least partially surround the trench isolation region, the first and second doped regions may have the same conductivity type, and the second doped region may have a higher conductivity than the first doped region.

Low noise semiconductor devices

In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.

Schottky diodes having metal gate electrodes and methods of formation thereof

A semiconductor device includes at least one source region and at least one drain region. A plurality of fins extend between a source region and a drain region, wherein at least one fin has a different width than another fin. At least one gate is provided to control current flow through such fins. Fin spacing may be varied in addition to, or alternative to utilizing different fin widths.

Semiconductor device having different fin widths

An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator.

Noise reduction in semiconductor devices

Growing community of inventors

Munich, Germany

Domagoj Siprak