Samsung Electronics Co., Ltd.

Dokyung Kim

Jong-Kon Bae

Sooyoung Woo

Junho Park

JunHo Park

Chulho Kim

Yanghyo Kim

Wonsik Kang

Chiho Cha

Jeung Hwan Lee

A display driver integrated circuit including a logic circuit configured to receive image data from a host and an image cyclic redundancy check (CRC) unit configured to perform a CRC operation on output data of the logic circuit and transmit the performed result to the host may be provided. Additionally, a timing controller including a logic circuit configured to receive image data from a host and an image CRC unit configured to perform a CRC operation on output data associated with the logic circuit and configured to transmit the performed result to the host may also be provided. Further, a display device including a display panel, a display driver integrated circuit configured to drive the display panel and an image CRC unit configured to perform a CRC operation on output data of the logic circuit and transmit the performed result may be provided.

Display driver integrated circuit and display device having the same

A display driver integrated circuit is provided which includes a first line buffer which receives first pixel data of an odd lane in response to an external clock and outputs the first pixel data in response to an internal clock; a second line buffer which receives second pixel data of an even lane in response to the external clock and outputs the second pixel data in response to the internal clock; a line buffer controller which receives display data by the two pixel data to output the first and second pixel data; a data merger which merges the first pixel data output from the first line buffer and second pixel data output from the second line buffer; and an image data processing block which processes the merged pixel data, wherein a frequency of the internal clock is lower than a frequency of the external clock.

Display driver integrated circuit and display data processing method thereof

A display driver integrated circuit which includes a distributor configured to output display data; a plurality of first-in first-out (FIFO) memories configured to receive the display data from the distributor according to an external clock and output the display data in response to an internal clock; and a plurality of graphics memories configured to receive the display data from the FIFO memories.

Display driver integrated circuit including first-in-first-out (FIFO) memories configured to receive display data from a distributor and output the display data to graphics memories a display system having the same, and a display data processing method thereof

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Yongin-si, South Korea

Dokyung Kim