Lg Display Co., Ltd.

Samsung Electronics Co., Ltd.

Lg Chem, Ltd

Display Co., Ltd.

Dohan Kim

Jungkeun Kim

Hyoseok Kim

Min Ro Yun

Seunghee Yoon

Jeongdae Seo

Hyeseung Kang

Insu Choi

Changwoo Lee

Namhyung Kim

Wanpyo Hong

Shinhan Kim

Deokho Seo

Daejeong Kim

Heungwoo Choi

Jinmin Bang

Sergey Zhidkov

Seonkeun Yoo

Changmin Lee

Wonjae Shin

Kwanho Kim

Beom Kon Kim

Minsu Kim

Jaeho Kim

Chanik Park

Sunghoon Joo

Jaehun Cho

Ilguy Jung

Kihuk Lee

Byungsoo Kim

Hoyoung Lee

Ki-Woog Song

Jonghoon Won

JungSoo Park

Kwan Ho Kim

ChangWook Han

Seongsu Jeon

EunJung Park

SeungRyong Joung

Jun Yeob Lee

Hajoong Park

Jungsoo Park

Yoonheung Tak

Hanbyeol Seok

Sang Bae Han

YoonHeung Tak

Chinam Kim

Taewoo Jeon

KwanHo Kim

Eunjung Park

Taekyeong Ko

Byeongnoh Kim

Bobae Kim

Kyeongjin Cho

Min Seong Yun

KyouSic Kim

Seong-Shik Moon

Daewon Ryu

Jaein Song

Seungryong Joung

Seunkeun Yoo

A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

Memory system, operating method of the same, and controller of memory device

A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

Memory device including address table and operating method for memory controller

Various embodiments of the present invention relate to an apparatus and method for processing images in an electronic device. The electronic device includes: a memory; an image sensor; an image control circuit operatively connected to the image sensor; and an image signal processor operatively coupled to the image control circuit. The image control circuit can store a plurality of frames received through the image sensor in the memory, transmit the plurality of frames stored in the memory to the image signal processor, and, when the number of frames that have not been transmitted to the image signal processor among the plurality of frames obtained from the image sensor exceeds a designated number, remove the frames that have not been transmitted to the image signal processor from the memory.

Electronic device for processing images and method for operating same

An electronic device is provided. The electronic device includes an image sensor including a plurality of pixels, an AP processing unit, a memory, and a control unit. Each pixel included in the plurality of pixels includes a plurality of photodiodes and a microlens. The control unit provides at least one of a first piece of AF data and a second piece of AF data to the AF processing unit, and the AF processing unit may execute a first phase autofocus (PAF) operation based on the first piece of AF data or execute a second PAF operation based on the second piece of AF data.

Electronic device, and method for performing autofocus by rotating or reordering AF data

An organic electroluminescence device including an anode, a cathode and a light-emission layer. The light-emission layer includes a stack of a blue light-emission layer and a red/green light concurrent-emission sub-stack. Further, the red/green light concurrent-emission sub-stack includes a stack of a red light-emission layer and a green light-emission layer. The red light-emission layer contains a red host compound including an arylamino group-substituted spirobisfluorene compound. Further, the green light-emission layer contains a green host compound including a mixture between a first green host compound and a second green host compound. Also, the first green host compound includes a bis-carbazole based compound, and the second green host compound includes a carbazole-based compound.

Organic electroluminescence device

A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

Memory device, memory module including the memory device, and operating method of memory controller

Disclosed is a benzazole derivative having a heteroaryl group, wherein the benzazole derivative having the heteroaryl group is represented by Chemical Formula 1. Also disclosed is an organic electroluminescence device including an organic layer containing the benzazole derivative having the heteroaryl group:

Benzazole derivative having heteroaryl group and organic electroluminescence device including the same

An organic light emitting display device is provided. The organic light emitting display device may include at least one light emitting part between al anode and a cathode, and the at least one light emitting part having at least one organic layer and a light emitting layer, wherein the at least one organic layer comprises a compound represented by Chemical Formula 1 or 2.

Organic light emitting display device

An organic light emitting display device is provided. The organic light emitting display device includes at least two or more light emitting parts between an anode and a cathode and each having a light emitting layer. At least one of the at least two or more light emitting parts includes an organic layer. The organic layer is formed of a compound comprising a functional group that reacts with alkali metals or alkali earth metals and a functional group with electron transport properties.

An organic light emitting display device is provided. The organic light emitting display device may include at least one light emitting part between an anode and a cathode, and the at least one light emitting part having at least one organic layer and a light emitting layer, wherein the at least one organic layer comprises a compound represented by Chemical Formula 1 or 2.

Disclosed herein is a compound for electron transport material and an organic light emitting diode including the same. The compound for electron transport material is represented by the following Formula 1. Since the compound for electron transport material, as represented by Formula 1, contains a triazine structure, the compound has high electron mobility and is thus suitable as an electron transport material. The organic light emitting diode includes an electron transport layer formed of the compound as represented by Formula 1 and thus can have increased lifespan.

Compound for electron-transport material and organic light emitting diode including the same

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

Memory device capable of outputting fail data in parallel bit test and memory system including the memory device

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

Various embodiments may provide an electronic device including a memory, a first image sensor circuit, a second image sensor circuit, and at least one processor, operatively connected to the first image sensor circuit and the second image sensor circuit, configured to control the first image sensor circuit to output first frame data associated with a first field of view at a first frame rate from a first time point to a second time point, and store the first frame data in the memory, control the second image sensor circuit to output second frame data associated with a second field of view at the first frame rate from a third time point after the second time point to a fourth time point, and store the second frame data in the memory, obtain the stored first frame data and the stored second frame data from the memory.

Electronic device including a plurality of image sensors and method for thereof

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Memory device skipping refresh operation and operation method thereof

Growing community of inventors

Gyeonggi-do, South Korea

Dohan Kim