Samsung Electronics Co., Ltd.

Doh-Young Kim

Phil-Jae Jeon

A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.

Lock detector and delay-locked loop having the same

A delay-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled delay line and a coarse lock detector. The phase frequency detector generates an up signal and a down signal corresponding to phase and frequency differences between an input clock signal and a feedback signal. The charge pump receives the up signal, the down signal and a coarse lock detection signal to generate a current signal. The loop filter receives and filters the current signal through a low-pass filter to generate a direct voltage signal. The voltage controlled delay line receives the input clock signal and the direct voltage signal to generate the feedback signal and control signals. The coarse lock detector receives the control signals to generate the initialization signal and the coarse lock detection signal to adjust Td within Tin/2&#x3c;Td&#x3c;2&#xd7;Tin when Td&#x2267;2&#xd7;Tin or Td&#x2266;Tin/2.

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Seoul, South Korea

Doh-Young Kim