Intel Corporation

Sonics, Incorporated

Doddaballapur N Jayasimha

Christopher J Hughes

Samantika S Sury

Jonas Svennebring

Yen-Cheng Liu

David A Koufaty

Stephen R Van Doren

Akhilesh Kumar

Jeremy Chan

Mani Ayyar

Liping Guo

Ioannis T Schoinas

Joseph Nuzman

Niall D McDonnell

Jose Andy Vargas

Eric R Delano

Phanindra Mannava

Stephen J Robinson

James R Anderson

Kshitij Arun Doshi

Vedvyas Shanbhogue

Murugasamy K Nachimuthu

John Joseph Browne

Srinivas Chennupaty

Victor W Lee

Drew Eric Wingard

Raghu R Kondapalli

Jong Soo Park

Ilango S Ganga

Lokpraveen B Mosur

Swadesh Choudhary

Patrick Fleming

Jay S Tomlinson

Mark Debbage

Stephen Doyle

Stephen W Hamilton

Lingxiang Xiang

Ajit Krisshna Nandyal Lakshman

Ioannis Yannis Schoinas

Robert Cone

Raghu Ram Kondapalli

In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.

System, apparatus, and method for streaming input/output data

In one embodiment, a fabric circuit is to receive requests for ownership and data commits from an agent. The fabric circuit includes a control circuit to maintain statistics regarding the requests for ownership and the data commits and throttle the fabric circuit based at least in part on the statistics. Other embodiments are described and claimed.

System, apparatus and method for controlling traffic in a fabric

Disclosed embodiments relate to atomic memory operations. In one example, a method of executing an instruction atomically and with weak order includes: fetching, by fetch circuitry, the instruction from code storage, the instruction including an opcode, a source identifier, and a destination identifier, decoding, by decode circuitry, the fetched instruction, selecting, by a scheduling circuit, an execution circuit among multiple circuits in a system, scheduling, by the scheduling circuit, execution of the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance, and executing the decoded instruction, by the execution circuit, to: atomically read a datum from a location identified by the destination identifier, perform an operation on the datum as specified by the opcode, the operation to use a source operand identified by the source identifier, and write a result back to the location.

Instructions for remote atomic operations

A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

Technology for moving data between virtual machines without copies

Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Remote atomic operations in multi-socket systems

Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

Spatial and temporal merging of remote atomic operations

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Method, system, and apparatus for dynamic reconfiguration of resources

A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.

Credit flow control scheme in a router with flexible link widths utilizing minimal storage

An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

Apparatus and methods for an interconnect power manager

A method for generating headers in packetized protocols for a flexible routing network for a Network on a Chip (NoC) architecture includes generating packets based on transmission traffic received from an initiator or a target connected to a routing network that connects disparate initiators and targets. Logic to generate the packets is in an interface located between the initiator or the target and the routing network. A header portion of a packet is variable in length and includes a header payload and header control information. Each of the header portion and the body portion includes one or more standard sized transmission units. The size of the transmission units and width of the header payload are determined by logic included in the interface. The width of the header payload is determined based on orthogonal groups with each of the orthogonal groups being associated with targets sharing an initiator thread.

Efficient header generation in packetized protocols for flexible system on chip architectures

Growing community of inventors

Saratoga, CA, United States of America

Doddaballapur N Jayasimha