Skhynix Inc.

Samsung Electronics Co., Ltd.

Do Yun Lee

Chang Hyun Kim

Jae Jin Lee

Min Chang Kim

Hun Sam Jung

Dong-Won Kim

Geon Ho Lee

Baek Gyu Kwon

Bo-Kyun Kim

Sang Wook Kim

Yong Woo Lee

Hoe Kwon Jung

Jung Hwan Kim

Jong Su Jeon

Hong Seok Ko

Seung Youp Lee

Jong-Hun Sung

A washing machine including a plurality of washers may include a fixing bracket coupled to a front of a first housing in which a first tub is disposed and a front of a second housing in which a second tub is disposed, to prevent the first housing and the second housing from being separated from each other.

Washing machine

A washing machine including a cabinet with an opening, a door that opens and closes to uncover and cover the opening, respectively, and a door locking device that selectively restrains a motion of the door when the door is closed. This configuration may be used to prevent the door from opening when, for example, the washing machine is in operation. In addition, a structure of a front portion of the opening may facilitate loading and unloading of laundry.

Disclosed is a washing machine including a first housing in which a first tub is disposed and a second housing in which a second tub is disposed. In the washing machine, a drain pump of the second tub may be disposed at the first housing to efficiently utilize internal spaces of the first housing and the second housing.

A semiconductor device may include an operation control circuit configured to generate a detection signal based on an internal temperature of the semiconductor device. The semiconductor device may include an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the detection signal.

Semiconductor device and semiconductor system

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.

Data I/O circuits and semiconductor systems including the same

A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal. The test data comparison circuit may generate a test result signal by comparing data output from the first data storage region, the second data storage region, the first data transfer circuit, and the second data transfer circuit and output the test result signal to the external equipment through the input/output pad.

Semiconductor device including chips capable of comparing data

A memory module may include a plurality of memory groups configured to include a plurality of memory packages, respectively, and input/output data through input/output pins. The memory module may include a control circuit configured to activate one or more of the plurality of memory groups on a basis of an address signal. The memory module may include a multiplexer circuit configured to couple the memory group activated on the basis of the address signal to input/output buses of the memory module.

Memory module including plurality of memory packages with reduced power consumption

A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive signals from the first chip to generate a latch address based on the received signals from the first chip.

Semiconductor device

A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.

Memory device and system including the same

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

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Yongin-si, South Korea

Do Yun Lee