Skhynix Inc.

Korea Research Institute of Chemical Technology

Do Sun Hong

Jung Hyun Kwon

Donggun Kim

Yong Ju Kim

Wongyu Shin

Seunggyu Jeong

Young Kyu Hwang

Dong Won Hwang

Won Gyu Shin

Jong San Chang

U Hwang Lee

Pravin Pandharinath Upare

Jin Woong Suh

Seung Gyu Jeong

Jae Sun Lee

Kyung Ho Cho

Sang Gu Jo

Su Kyung Lee

Sungeun Lee

Jingzhe Xu

An error correction method includes performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer in a second operation mode.

Error correction method of a memory system

A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Memory systems and methods of correcting errors in the memory systems

A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.

Read time-out managers and memory systems including the read time-out managers

A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.

Semiconductor memory system and method of repairing the semiconductor memory system

A data transmission system includes a data transmitter and a data receiver. The data transmitter outputs 'N'-bit transmission data (where 'N' denotes a natural number which is equal to or greater than two). The data receiver receives the &#x2018;N&#x2019;-bit transmission data through &#x2018;N&#x2019;-number of data transmission lines. The data receiver transmits a re-transmission request signal to the data transmitter when the &#x2018;N&#x2019;-bit transmission data inputted to the data receiver are erroneous data. The data transmitter divides the &#x2018;N&#x2019;-bit transmission data in response to the re-transmission request signal and operates in a first data re-transmission mode so that the divided transmission data are resent, together with first ground data, to the data receiver.

Data transmission systems and data transmission methods of suppressing data error occurrences due to crosstalk

A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.

Memory systems performing reconfigurable error correction operation using ECC engine with fixed error correction capability

A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

Memory system including a delegate page and method of identifying a status of a memory system

An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.

Apparatuses and methods of distributing addresses in memory devices for mitigating write disturbance

A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

Memory apparatus and method of wear-leveling of a memory apparatus

The present invention relates to a method for preparing mannitol which includes performing the hydrogenation of fructose in the presence of a Cu-based nanocomposite catalyst, for example, a nanocomposite catalyst of CuO(x)/SiO2(100-x) (wherein x is a real number from 20 to 90), using butanol as a solvent.

Method for preparation of mannitol from fructose using butanol as solvent

In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

Memory module, system including the same

The present invention relates to a method for preparing for a furan derivative from biomass, comprising step (1) of preparing 5-hydroxymethylfurfural by reacting biomass and a solid acid catalyst in butanol; and step (2) of preparing a furan derivative by reacting the butanol solution of 5-hydroxymethylfurfural, obtained in step (1), with a hydrogenation catalyst.

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Icheon-si, South Korea

Do Sun Hong