Yonsei University

Coupang, Corporation

Do Hyeon Kim

Jae Hyun Kim

Young Jin Kim

Chang Hyun Lee

Sang Hyup Lee

Suk Min Ahn

Eui Young Chung

Min Jung Cho

Seong Jae Eom

Disclosed are a method for designing a cache memory structure of an artificial intelligence accelerator and an apparatus therefor. A method for designing a structure of a cache memory of an accelerator in a cache memory structure designing apparatus is a cache memory structure designing method including a memory access information extracting step of extracting a memory address of a cache memory accessed by a processing element array (PE array) at every time stamp for an application input to the accelerator, a memory access pattern determining step of determining a memory access pattern for the application based on the memory addresses of the cache memory accessed over time, and a cache structure design step of deriving a cache memory structure using a cache structure design model trained in advance based on a memory access pattern and generating cache structure design information for the cache memory structure.

Method and apparatus for designing cache memory structure based on artificial intelligence

Provided is an information providing method of an electronic apparatus, the method including identifying sales information of an item that is for sale through the network, identifying whether it is necessary to provide item sales management information based on the identified sales information of the item, and, when it is necessary to provide the item sales management information, providing the item sales management information generated based on the sales information of the item.

Electronic device for providing product sale managing information and method thereof

Growing community of inventors

Seoul, South Korea

Do Hyeon Kim