Metisx Co., Ltd.

Xcena Inc.

Do Hun Kim

Kwang Sun Lee

Ju Hyun Kim

Kee Bum Shin

Kwangsun Lee

Keebum Shin

Jin Yeong Kim

Jae Wan Yeon

Sungju Han

Ji Hun Choi

It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

Cache memory device and method for implementing cache scheduling using same

As one aspect of the present disclosure, an electronic device is disclosed. The electronic device comprises a receiving unit for receiving a command from an external source, a first buffer for storing a first data value, and an operation engine for loading the first data value from the first buffer in response to the command and performing an operation based on a predetermined calculation formula on the loaded first data value, wherein the first data value is at least one of a result data value obtained by the operation engine previously performing an operation based on the predetermined calculation formula or a query data value to be used for an operation based on the predetermined calculation formula.

Electronic device with buffered operation engine and method for performing calculation using same

As one aspect of the present disclosure, a byte-addressable device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor, the volatile memory device, and a non-volatile storage device, wherein the controller may be further configured to communicate with the volatile memory device and the non-volatile storage device based on address information included in a request received from the host processor.

Byte-addressable device and computing system including same

As one aspect of the present disclosure, an electronic device is disclosed. The device includes: a plurality of clusters, wherein each of the plurality of clusters comprises a plurality of cores; mailboxes uniquely corresponding to each of the plurality of clusters; and a system bus, wherein the inter-process communication may be performed between a sending core and a receiving core of the plurality of cores, and if the sending core and the receiving core are included in the same cluster, a mailbox corresponding to the same cluster may be configured to perform the inter-process communication without going through the system bus, and if the sending core and the receiving core are included in different clusters, mailboxes corresponding to each of the different clusters may be configured to perform the inter-process communication via the system bus.

Electronic device including hardware architecture for supporting inter-process communication and method for performing inter-process communication

A method for processing multiple transactions converted from a single transaction is provided, which is performed by a processor including at least one core and includes converting a first transaction conforming to an instruction according to an instruction set architecture (ISA) into a plurality of second transactions conforming to the register size of the core, and transferring, by the load-store unit (LSU) of the core, the plurality of second transactions to the cache, in which the LSU may be configured to further transfer, to the cache, conversion information indicating whether the plurality of second transactions are converted from the first transaction.

Method for processing multiple transactions converted from single transaction in processor, and processor for performing same

The present disclosure relates to a manycore system which includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each of the plurality of clusters includes a program memory configured to store a program associated with the job requested to be offloaded, a plurality of cores configured to execute one or more threads associated with the job, and a management module configured to allocate one or more tasks associated with the job to the plurality of cores based on job loads of the plurality of cores, and control thread execution corresponding to the one or more allocated tasks. Each core includes thread areas configured to independently store and track an execution state of each thread executed on the core, and each thread executed on the core is independently executed using a separate thread area.

Manycore system

A multiprocessor system may include a plurality of processors including a first processor and a second processor; a first cache memory corresponding to the first processor; a second cache memory corresponding to the first processor and the second processor and storing a plurality of cache lines; and a controller manages data stored in the second cache memory. The second cache memory includes at least one first cache line in which data is written by the first processor and at least one second cache line in which data is written by the second processor. The controller: receives a command associated with a data update from the first processor, and in response to the command, sets the first cache line as a clean cache line or an invalidated cache line while not setting the second cache line as a clean cache line or an invalidated cache line.

Multiprocessor system and data management method thereof

The present disclosure relates to a manycore system capable of asynchronous execution of a plurality of threads. The manycore system includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each cluster includes a plurality of cores configured to execute a plurality of threads associated with a plurality of tasks included in the job and a management module configured to control asynchronous execution of the plurality of threads by the plurality of cores. Each core includes a plurality of fetch units configured to fetch, from the program memory, instructions associated with threads executed on the cores, one or more execution units configured to execute operations associated with the threads executed on the cores, and a plurality of load and store units configured to load and store data associated with the threads executed on the cores.

Manycore system for performing execution of multi-threads in asynchronous manner

A multi-threading processor is provided, which includes a cache including a memory and a controller, and a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads, in which the core is configured to determine an occurrence of a data hazard for the plurality of threads and stall operations of the plurality of threads, receive, from the cache, hint information instructing a first thread of the plurality of threads to operate, and initiate an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained.

Multi-threading processor and operating method thereof

A method for processing multiple transactions converted from a single transaction related to each of a plurality of threads is provided, in which the method is performed by a processor including at least one core and includes converting a first transaction related to at least one of the plurality of threads into a plurality of second transactions, transferring, by a load-store unit (LSU) of the core, the plurality of second transactions to a subordinate or a cache, receiving, by the LSU, a plurality of data units related to the second transactions from the subordinate or the cache, and merging, by the LSU, the plurality of data units, in which the LSU is configured to further transfer interleaving deactivation information that causes the subordinate or the cache to deactivate interleaving.

A multiprocessor system includes a plurality of processors, a first cache device corresponding to a first processor of the plurality of processors and including a first cache memory configured to store a plurality of first cache lines, and a second cache device at different level than the first cache device, corresponding to the plurality of processors, and including a second cache memory that stores a plurality of second cache lines, in which the first cache device is configured to, in response to a request related to data access, search the first cache memory for data, and the second cache device is configured to, in response to the data cache-missed in the first cache memory, search the second cache memory for data, and in response to the data cache-hit in the second cache memory, set cache line of the second cache memory corresponding to the data as clean cache line.

Provided is a cache memory device including a command reception unit for packetizing each of read commands and write commands and classifying them as even or odd; a cache scheduler comprising a first reorder scheduling queue for receiving commands classified as even numbers from the command reception unit and scheduling the commands classified as even numbers for cache memory accesses and a second reorder scheduling queue for receiving commands classified as odd numbers from the command reception unit and scheduling the commands classified as odd numbers for cache memory accesses; and an access execution unit for performing cache memory accesses via a cache tag to scheduled commands classified as even numbers and scheduled commands classified as odd numbers.

Growing community of inventors

Yongin-si, South Korea

Do Hun Kim