Skhynix Inc.

Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Hyundai Motor Company

Jntg Co., Ltd.

Kia Motors Corporation

Autoliv Development Ab

Samsung Led Co., Ltd.

Korea Electronics Technology Institute

Newtree Co., Ltd.

Toray Chemical Korea Incorporated

Biocare Co., Ltd.

University Industry Cooperation Foundation Korea Aerospace University

Jntc Co., Ltd.

Do Hun Kim

Hyung Suk Kim

Hun Joo Hahm

Young Sam Park

Ju Hyun Kim

Seong Yeon Han

Dae Yeon Kim

Jin Yeong Kim

Dae Hyun Kim

Kwang Sun Lee

Shi Hwa Lee

Taek Sun Shin

Eun Sook Lee

Jy Young Jyoung

Seong-Yong Hwang

Sung-Kyu Shim

Kang Eun Lee

Ji Eun Nam

Tae Yong Ryu

Gi Jo Jeong

Tae Nyun Kim

Eun Chong Kim

Na Hee Kang

Jae Wan Yeon

Sang Hoon Lee

Young Min Park

Kyung-Min Kim

Ji Won Lee

Seung Hwan Chung

Seung-Hwa Ha

Dong Hyeon Lee

Se Ki Park

Seong Yong Hwang

Jae Sul An

Jae Han Park

Joon Ho Song

Chang Yong Son

Yong-hoon Kwon

Byung Seo Yoon

Tae Hyung Kim

You Ra Kim

Hyung Min Kim

Dong Hoon Kim

Dong Jun Lee

Jae Young Lee

Jung Wook Lee

Hyoung-Joo Kim

Jeong Hwan Kim

Jin Hong Ahn

Jee Wook Huh

Sang Yun Lee

Doo Hyun Kim

Kang-Woo Lee

Kie Youn Jeong

Sun Hee Kim

Hyo Seok Kim

Young Keun Lee

Jae-Kwan Hwang

Tae Ik Gwon

Hyun Suk Lee

Eung Seo Kim

Ju Youn Son

Won Jin Kim

In Sun Hwang

Ju Young Yoon

Jae Haeng Yoo

Dae Young Kwak

Chang Hoon Baek

Hyun Su Park

Raj Narayana Gadde

Sang Heon Ye

Soon Bok Lee

Joong Hyun Kim

Byung-Gon Kum

Yong Seong Kim

Da Woon Kim

Choul Ho Lee

Hyun Hyang Kim

Sung Min Yang

Sang Jin Choi

Heechul Chung

Hyun-Hwa Song

Bong Hwan Park

Ji Sang Seo

Jin Woong Cho

Myoung Soo Choi

Jae-hwan Jeon

Jae Youn Chung

Jin Ho Ahn

Dong Jin Sohn

Dae Ki Hong

Seog Ho Lim

Hyoung Suk Jang

In Je Sung

Hyun Mo Kang

Hyun Hwa Song

Jong Sik Ryu

Hae Ji Lee

You Jin Seo

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Controller and memory system

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Memory controller, storage device including the memory controller, and method of operating the memory controller and the storage device

An operation method includes buffering data chunks to be programmed in the multi-level cells in a write buffer; backing up at least one backup data chunk of the data chunks to a backup memory; determining a program sequence of the data chunks, the program sequence for programming a non-backup data chunk among the data chunks to the multi-level cells through a second step program operation of the multi-step program operation; and controlling the memory device to program the data chunks in the multi-level cells, based on the program sequence, by performing first and second step program operations of the multi-step program operation in a first page of the multi-level cells, the second step program operation performed in the first page later than another first step program operation performed in a second page subsequent to the first page.

Controller and operation method thereof

An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device

A lower sheet disposed below a display panel includes a heat radiation layer having a first side and a second side facing the first side. A first film layer is disposed on the first side of the heat radiation layer. A second film layer is disposed on the second side of the heat radiation layer. A first resin layer is disposed between the heat radiation layer and the first film layer. A second resin layer is disposed between the heat radiation layer and the second film layer. A sealing layer is disposed on lateral sides of the heat radiation layer. The sealing layer directly contacts an entirety of the lateral sides of the heat radiation layer, and directly contacts at least a portion of lateral sides of the first resin layer and the second resin layer.

Sheet disposed below panel, and display device including the same

A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.

Memory controller, memory system, and operating method thereof

Provided is a gas diffusion layer, in which a microporous layer has an inner wall of through passages and a region adjacent to the through passages containing a greater amount of a water-repellent binder resin than a region not adjacent to the through passages, and thus water formed by an electrochemical reaction is effectively discharged from the gas diffusion layer. When the gas diffusion layer of the present invention is used, an optimal water management may be possible for smooth operation under all humidity conditions including a high humidity condition and a low humidity condition, and thus a fuel cell having improved cell performance may be obtained.

Gas diffusion layer including microporous layer having through passages and/or concentration gradient of water-repellent resin in thickness direction, and fuel cell including the same

Disclosed are a carbon substrate for a gas diffusion layer of a fuel cell, a gas diffusion layer employing the same, an electrode for a fuel cell, a membrane electrode assembly for a fuel cell, and a fuel cell, wherein the carbon substrate includes a plate-shaped substrate having an upper surface and a lower surface opposite the upper surface, and the plate-shaped substrate includes carbon fibers arranged to extend in one direction (extend unidirectionally) and a carbide of an organic polymer located between the carbon fibers to bind the carbon fibers to each other. Since the carbon substrate according to the present disclosure includes carbon fibers aligned in at least one direction selected from a machine direction (MD) and a cross-machine direction (CMD) by controlling the alignment of carbon fibers, the carbon substrate has excellent mechanical strength, particularly, bending strength, even if its thickness is thin, and thus it is possible to effectively prevent the intrusion phenomenon of the gas diffusion layer into the flow path of the metal separator, and has excellent gas flow characteristics.

Carbon substrate comprising carbon fibers unidirectionally aligned, and gas diffusion layer employing same

A carbon substrate for a gas diffusion layer of a fuel cell, the carbon substrate being a porous carbon substrate having a first surface and a second surface opposite the first surface, the carbon substrate includes a plurality of carbon fibers arranged irregularly to form a non-woven type and a carbide of an organic polymer located between the carbon fibers to bind the carbon fibers to each other, the carbide has a graphite structure, and the carbon substrate has a Bragg diffraction angle 2θ of less than 26.435° and a interplanar distance d(002) of less than 3.372 Å, a gas diffusion layer employing the same, an electrode for a fuel cell, a membrane electrode assembly for a fuel cell, and a fuel cell. When the gas diffusion layer is manufactured using the carbon substrate according to the present disclosure, cell voltage characteristics of the fuel cell may be greatly improved.

Graphitized carbon substrate and gas diffusion layer employing same

The present technology relates to an electronic device. A memory controller that increases a hit ratio of a cache memory includes a memory buffer configured to store command data corresponding to a request received from a host, and a cache memory configured to cache the command data. The cache memory stores the command data by allocating cache lines based on a component that outputs the command data and a flag included in the command data.

Memory controller for allocating cache lines and method of operating the same

A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.

A controller for controlling a memory device is provided to include: a request receiver configured to receive a request including a logical address from a host; a dependency checker configured to acquire the request from the request receiver and check a dependency of the request; a map manager configured to generate a command including a physical address mapped to the logical address of the request in response to a result of checking that the request has no dependency on the prior incomplete request; and a command submitter configured to provide the memory device with the command generated by the map manager, wherein the request receiver, the dependency checker, the map manager and the command submitter are structured to configure a data pipeline such that operations of the request receiver, the dependency checker, the map manager, and the command submitter deliver are performed in series.

Controller for performing data input/output operation and memory management operation at the same time and operation method thereof

Growing community of inventors

Gyeonggi-do, South Korea

Do Hun Kim