Skhynix Inc.

Do Hong Kim

Duck Hwa Hong

Sang Hyun Ku

Min Ho Seok

So Yoon Kim

Woongrae Kim

Sang Il Park

Jong Seok Han

Kyung Mook Kim

Sang Woo Yoon

Kwang Soo Kim

Disclosed is a semiconductor device including a first cell mat including memory cells connected to a first bit line, a second cell mat including memory cells connected to a second bit line, a sense amplifier configured to amplify a difference in voltages between the first bit line and the second bit line, and a control circuit configured to differently adjust timing at which the first bit line and the second bit line are connected to or disconnected from the sense amplifier.

Semiconductor device and operating method of semiconductor device

A memory device includes a plurality of word lines; and a row control circuit configured to: drive, in response to a precharge command, a selected word line of the word lines such that a voltage level of the selected word line decreases from a first voltage level to a second voltage level during a first section, stays at the second voltage level during a second section and decreases from the second voltage level to a third voltage level during a third section, and keep the second section at a preset time amount, or change the second section to a time amount defined by an input of an active command according to a mode control signal.

Memory device performing precharge operation, and operating method thereof

A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.

Memory including row circuit and operation method thereof

A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

Devices for performing a refresh operation based on power control operation

A semiconductor memory apparatus includes a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or decouple output nodes of the first sense amplifier driving voltage generation unit and the second sense amplifier driving voltage generation unit according to the switching control signal.

Growing community of inventors

Hwaseong-si Gyeonggi-do, South Korea

Do Hong Kim