Samsung Electronics Co., Ltd.

Do-Chan Choi

Kyung-Tae Kim

Tae-Sung Jung

Ejaz Ul Haq

Woung-Moo Lee

Syed Ali

Myung-jae Kim

Dong-jae Lee

Kyeong-tae Kim

Yong-Sik Seok

Dong-soo Jun

Jong-Chang Son

Oh-Seung Kwon

Young-Gwon Choi

Chan-Sok Park

A plurality of memory types are distinguished from one another in memory systems containing a plurality of memory types by applying an input signal to the memory system containing the plurality of memory types and detecting differing outputs from the plurality of memory types during a predetermined time period after the input signal is applied. Extended data output (EDO), dynamic random access memories (DRAM) are thereby distinguished from fast page mode (F/P) DRAM. Similarly, nonvolatile memory such as DRAM interface flash memory (DIFM) are distinguished from conventional DRAMs.

Systems and methods for distinguishing between memory types

Nonvolatile memory devices and methods include an array of nonvolatile memory cells which are arranged in a plurality of rows and a plurality of columns. A plurality of word lines are also included, a respective one of which is connected to the nonvolatile memory cells in a respective one of a plurality of columns. A plurality of lockable cells are also included. A respective one of the lockable cells is connected to a respective one of the plurality of word lines. Each of the lockable cells stores therein a first or a second binary value. The first binary value indicates that nonvolatile memory cells which are connected to the corresponding column of word lines cannot be erased or reprogrammed. The second binary value indicates that nonvolatile memory cells which are connected to the corresponding column of words lines can be erased or programmed.

Nonvolatile memory devices including lockable word line cells

An electrically erasable and programmable nonvolatile memory device (EEPROM) such as a flash memory, is pin compatible with a dynamic random access memory device (DRAM), such that flash memory may be connected to a DRAM bus. Preferably, the flash memory is read and write timing-compatible with the DRAM read and write signals and is also preferably block read and block write timing compatible with DRAM block read and block write signals. The flash memory accepts signals to perform sleep and erase functions from signal lines of a DRAM bus which are not used by a DRAM. In order to perform a block erase, which is a characteristic of flash memory, the device preferably accepts an instruction to perform a block erase from signal lines of a DRAM bus which are not used by a DRAM and a block address for the block erase from the most significant bit address lines of the DRAM bus.

Nonvolatile semiconductor memory which is connectable to a DRAM bus

Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

Self-contained reprogramming nonvolatile integrated circuit memory

An input protection circuit for a semiconductor memory device senses when the level of an external input signal drops below a reference voltage corresponding to a predetermined logic level, thereby enabling instant correction. The input protection circuit is interposed between an external power voltage terminal and an input terminal of the input buffer, and the external power voltage is transferred to the input terminal of the input buffer when the level of the external input signal applied to the input terminal drops below the predetermined logic level. The circuit includes an internal reference voltage generator which supplies a voltage having a level corresponding to the predetermined logic level and designed to compensate for a known device offset so that the external input signal applied to the input terminal can be instantly corrected.

Input protection circuit and method for semiconductor memory device

A high density semiconductor device is provided with an improved voltage pumping (bootstrapping) circuit. The voltage pumping circuit generates at an initial power-up state a first output voltage which is substantially identical to the memory device source supply voltage. The pumping circuit then pumps the first output voltage up to a second output voltage which is higher than the first output voltage. The pumping operation is achieved prior to or upon the semiconductor memory device being enabled in response to a series of pulses output from an oscillator.

Voltage pumping circuit for semiconductor memory devices

A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Method for manufacturing a semiconductor device

An address input buffer of a semiconductor memory device comprises an address input terminal, a column address switch, a row address switch, a column address latch connected to the column address switch, a row address latch connected to the row address switch, and an input buffer connected to the address input terminal, and the common node of the column address switch and the row address switch and controlled by an input buffer control signal. Thus, layout area can be reduced by buffering the row and column address input signals with one input buffer without separating the column and row address buffers.

Address input buffer

A MOS semiconductor device and the methods for constructing the device. The MOS device provided with first and second MOS transistors are formed on two identical wafer sections. The impurity region of the first transistor and a first group of gate side wall spacers are aligned to the gate of the first transistor. The impurity region of the second transistor and a second group of gate side wall spacers are aligned to the gate of the second MOS transistor. The second group of gate side wall spacers have a thickness different from that of the first group of gate side wall spacers.

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Seoul, South Korea

Do-Chan Choi