Microsoft Technology Licensing, LLC

Dmitry Pikulin

Roman Mykolayovych Lutchyn

Torsten Karzig

Georg Wolfgang Winkler

Chetan Vasudeo Nayak

Roman Bela Bauer

Christina Paulsen Knapp

Sebastian Heedt

Jonne Verneri Koski

Gijsbertus De Lange

Mason L Thomas

Bernard Van Heck

Esteban Adrian Martinez

Dominik André Gresch

John David Watson

Bas Nijholt

Rafal Maciej Rechcinski

Quantum devices formed from a single superconducting wire having a configurable ground connection are described. An example quantum device, configurable to be grounded, comprises a single superconducting wire having at least a first section and a second section, each of which is configurable to be in a topological phase and at least a third section configurable to be in a trivial phase. The quantum device further comprises semiconducting regions formed adjacent to the single superconducting wire, where the single superconducting wire is configurable to store quantum information in at least four Majorana zero modes (MZMs). The semiconducting regions formed adjacent to the single superconducting wire may be used to measure quantum information stored in the at least four MZMs.

Quantum devices formed from a single superconducting wire having a configurable ground connection

Examples described in this disclosure relate to gating a semiconductor layer into a quantum spin Hall insulator state, Certain examples further relate to using quantum spin Hall insulators as topological quantum qubits. Quantum spin Hall systems may rely upon the quantum spin Hall effect by causing a state of a matter to change from a certain phase to an inverted bandgap phase. In one example, the present disclosure relates to a device including a semiconductor layer comprising an active material. The device further includes a gate coupled to the semiconductor layer, where the semiconductor layer is operable in a quantum spin Hall insulator state by using electrons and holes from the active material in response to an application of an electric field to the semiconductor layer via the gate.

Gating a semiconductor layer into a quantum spin hall insulator state

A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Pre-screening and tuning heterojunctions for topological quantum computer

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Dmitry Pikulin