Huawei Technologies Co., Limited

Intel Corporation

Future Wei Technologies, Inc.

Dmitry Petrov

Lev Smolyar

Srikanth T Srinivasan

Sin Sim Tan

Haitao Mei

Bruce A Tennant

Ehud Nir

Zhonggui Xiang

Paul Madeira

The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

System and method for low jitter phase-lock loop based frequency synthesizer

An integrated circuit is described. The integrated circuit includes a first layer, a first clock line for carrying a first clock signal, and a second clock line for carrying a second clock signal. The second clock line runs alongside the first clock line for a distance. The integrated circuit includes a shield structure for shielding the clock line from crosstalk and/or other interference. The shield structure includes a shield wall extending from the first layer. The shield wall runs between the first and second clock lines for at least a portion of the distance. The shield structure may also include a shield cage extending from the first layer and surrounding the first and second clock lines for at least a portion of the distance. The shield cage has a plurality of openings. The shield cage and/or shield wall may be connected to the ground of an AC power supply.

Shield structure for a low crosstalk single ended clock distribution circuit

According to a first example aspect there is provided a charge pump circuit that includes a first chopper circuit configured to switch first and second chopper circuit outputs between first and second chopper circuit inputs at a chopping frequency, wherein successive input signals at the first chopper circuit input are output alternatively at the first and second chopper circuit outputs in successive cycles of the chopping frequency and successive input signals at the second chopper circuit input are output alternatively at the second and first chopper circuit outputs in successive cycles of the chopping frequency. A differential charge pump is configured to receive the signals output from the first and second chopper circuit outputs and produce corresponding first and second charge pumped signals.

Differential PLL with charge pump chopping

The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

PLL system and method of operating same

A method and voltage regulator comprises a generator that generates an error difference between a reference and regulated voltage. A clocked ADC samples the voltage as a digital stream. A DAC converts the stream to analog signal(s). A current source driven by the signal(s) generate(s) the regulated voltage. The generator may be an op-amp or comparator comprising a buffer and/or a latch. The N-bit ADC may be a &#x3a3;-&#x394; modulator or N 1-bit ADC latches. The N-bit DAC may comprise 1-bit DACs comprising a switched-capacitor summer and a one stage RC LPF. Sampling the error up-converts flicker noise to the clock frequency which the DAC filters out. The current source may comprise N transistors with gates driven by a signal and sources tied to an independent power supply. Each signal may be weighted by a DAC weight. The apparatus may comprise a decoupling capacitor between the regulated voltage and ground.

Low-noise sampled voltage regulator

Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed.

Limiting false wakeups of computing device components coupled via links

A circuit comprising a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals, and a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a feedback signal based on the one or more tuning signals, wherein generating the one or more tuning signals is based on the feedback signal.

Fully integrated differential LC PLL with switched capacitor loop filter

Apparatuses, methods, and articles of manufacture disclosing a filter with a plurality of convolver branches are described herein. Each of the plurality of convolver branches include a multiplier, integrator, and sampler and hold circuit. A sampled output of one branch may be fed back to another branch. Other embodiments may be described and claimed.

Programmable filter

Briefly, in accordance with one embodiment of the invention, a programmable filter may implement an infinite impulse response filter so that a transceiver in which the filter is utilized may be programmable to operate in one or more modes in accordance with one or more communication standards. The programmable infinite impulse response filter may replace one or more analog filters of the transceiver so that a desired filter response may be programmed by a baseband processor. Delay functions of an infinite impulse response filter may be implemented using feedback and multiplexing.

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Ottawa, Canada

Dmitry Petrov