Intel Corporation

Dmitry Messerman

Mohiuddin M Mazumder

Sourav Chakravarty

Yaakov Ben-Noon

Eli Chiprout

Michael Seltser

Gershon Hochman

Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a second rectangle that intersects the first rectangle, and if the second rectangle is found, performing a union of the first and second rectangles to generate a set of non-intersecting rectangles equivalent to the first and second rectangle.

Reorganizing rectangular layout structures for improved extraction

Embodiments of the present invention provide a method, apparatus and system for inductance modeling. According to some exemplary embodiments, a method for inductance modeling may include determining a plurality of two-dimensional mutual inductance values corresponding to a designated victim within a geometrical event and a plurality of designated attackers, respectively. Other embodiments are described and claimed.

Method, apparatus and system for inductance modeling in an electrical configuration

A method for extracting a reduced resistor network from an integrated circuit polygon layout is disclosed. The polygon layout includes a Manhattan polygon defined by a plurality of boundary lines. The method involves fracturing the Manhattan polygon along first and second division lines which extend from an intersection point at which first and second boundary lines intersect to define a 270 degree angle within the polygon. The first and second division lines extend parallel to the first and second boundary lines respectively and traverse the polygon so as to fracture the polygon into a number of rectangles. Each rectangle is substituted, or modeled, with a star configuration resistor arrangement, so as to construct a full resistor network. The method then enters an iterative sequence in which network reduction opportunities within the full resistor network are identified, and data concerning each network reduction opportunity is stored. The full resistor network is then reduced to a reduced resistor network by performing a series of reduction steps.

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Haifa, Israel

Dmitry Messerman