Intel Corporation

Elbrus International Limited

Perfectquote, Inc.

On Full Display, LLC

Dmitry M Maslennikov

Andrey Chudnovets

Sergey P Scherbinin

Jayesh Iyer

Boris A Babayan

Alexander Y Ostanevich

Sergey A Rozhkov

Alexander V Ermolovich

Denis G Motin

Aaron Snyder

Meghan Sylvester

Justin Sylvester

Vladimir Y Volkonsky

Pavel G Matveyev

Andrey Rodchenko

Boris V Shurygin

Yevgeniy M Astigeyevich

Marat Zakirov

Alexander I Kasinsky

Valentine G Tikhonov

A database interface system uses individual application program interfaces to receive, convert, combine, and normalize if necessary, datasets received from disparate sources. The datasets may include quotes from various insurance providers. The categorized and normalized data may be further processed for presentation via a user interface that allows selective display of the full combined datasets or graphically selected subsets of the full datasets.

Database interface system

Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a strand including a fork instruction introducing a first speculative assumption. A basing instruction to initialize a basing value of the strand before execution of a first instruction under the first speculative assumption. A determination of whether a second instruction under a second speculative assumption modifies a first memory address that is also modified by the first instruction under the first speculative assumption is made. The second instruction is not modified when the second instruction does not modify the first memory address. The second instruction is modified based on the basing value when the second instruction modifies the first memory address, the basing value to cause the second instruction to modify a second memory address different from the first memory address.

Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption

Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.

Apparatus and methods to support counted loop exits in a multi-strand loop processor

An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.

Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator

An apparatus includes a binary translator to hoist a load instruction in a branch of a conditional statement above the conditional statement and insert a speculation control of load (SCL) instruction in a complementary branch of the conditional statement, where the SCL instruction provides an indication of a real program order (RPO) of the load instruction before the load instruction was hoisted. The apparatus further includes an execution circuit to execute the load instruction to perform a load and cause an entry for the load instruction to be inserted in an ordering buffer, and where the execution circuit is to execute the SCL instruction to locate the entry for the load instruction in the ordering buffer using the RPO of the load instruction provided by the SCL instruction and discard the entry for the load instruction from the ordering buffer.

Method to do control speculation on loads in a high performance strand-based loop accelerator

An apparatus includes a first circuit to determine a real program order (RPO) of an eldest undispatched instruction from among a plurality of strands, a second circuit to determine an RPO limit based on a delta value and the RPO of the eldest undispatched instruction, an ordering buffer to store entries for instructions that are waiting to be retired, and a third circuit to execute an orderable instruction from a strand from the plurality of strands to cause an entry for the orderable instruction to be inserted into the ordering buffer in response to a determination that an RPO of the orderable instruction is less than or equal to the RPO limit.

Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor

Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a predicate dependency between a first compiled instruction and a second compiled instruction at a control flow join point, the second compiled instruction having different speculative assumptions corresponding to how the second compiled instruction will be executed based on an outcome of the first compiled instruction. A first strand is organized to execute a first instance of the second compiled instruction corresponding to a first one of the speculative assumptions, and a second strand to execute a second instance of the second compiled instruction corresponding to a second one of the speculative assumptions which is opposite to the first one of the speculative assumptions. The first instance of the second compiled instruction and the second instance of the second compiled instruction are executed in an asynchronous manner relative to each other and to the first compiled instruction.

Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture

Computer method of compiling a multi-way decision statement for VLIW processing is described. The method comprises: (a) generating profile data for a multi-way decision statement, such a s a switch statement; identifying at least one most probable alternative of the multi-way decision and a set of constants associated with the identified alternative using the profile data; determining a probable subset of the identified constants based on the profile data; constructing a conditional statement for the identified alternative using the probable subset of constants; and moving out the identified at least one alternative from the multi-way decision statement.

Computer method and apparatus for compilation of multi-way decisions

A method and system for use with VLIW processing architectures for avoiding redundant speculative computations in the compilation of the innermost loops. The method includes identifying a plurality of compiled flow paths, where each of the paths includes a plurality of conditions associated with the loop that permits transformation of the loop for more optimum execution. It is then determined whether the loop has an inductive variable and a conditional statement that depends on the inductive variable. It is also determined whether the loop set up values of the inductive variables to subsets, and at least one of which the conditional statement is a loop invariant. Finally, if conditions in the determination steps satisfy the conditions of one of the paths, the loop is transformed into two consecutive loops executable with a reduced set of values of the inductive variable.

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Moscow, Russia

Dmitry M Maslennikov