Intel Corporation

Dmitry Babokin

Vadim Sukhomlinov

Kshitij Arun Doshi

Michael Lemay

Areg Melik-Adamyan

Abhishek R Appu

Joydeep Ray

David M Durham

Ravi L Sahita

Mohan J Kumar

Vasanth Ranganathan

Baiju V Patel

Ankur N Shah

Ravishankar Iyer

Alex Nayshtut

Andrew J Herdrich

Sara S Baghsorkhi

Ben J Ashbaugh

Jr-Shian Tsai

Alexander Bachmutsky

Mingqiu Sun

Wei-Yu Chen

Ian M Steiner

Jeffrey D Chamberlain

Nilesh K Jain

Eric Dahlen

Mohammad R Haghighat

Mingwei Zhang

Amin Firoozshahian

Yeluri Raghuram

Anil Rao

Krishna Bhuyan

Leeor Peled

Harshad S Sane

Teck Joo Goh

Anup Mohan

Prathamesh Raghunath Shinde

Michael Prinke

Wenyong Huang

Daniel Fernando Gutson

Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load/store pipeline. The processing resource is operable to receive a memory access message including a pointer and a memory type identifier indicative of the pointer representing a generic pointer. The processing resource is further operable to output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type. The load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.

Providing native support for generic pointers in a graphics processing unit

Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

Bit matrix multiplication

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

Function as a service (FaaS) system enhancements

Embodiments are directed toward techniques to detect a first function associated with an address space initiating a call instruction to a second function in the address space, the first function to call the second function in a deprivileged mode of operation, and define accessible address ranges for segments of the address space for the second function, each segment to a have a different address range in the address space where the second function is permitted to access in the deprivileged mode of operation, Embodiments include switching to the stack associated with the second address space and the second function, and initiating execution of the second function in the deprivileged mode of operation.

Techniques to provide function-level isolation with capability-based security

Technologies are provided in embodiments for using compiling techniques to harden software programs from branching exploits. One example includes program instructions for execution to obtain a first encoded instruction of a software program, the first encoded instruction including a first opcode in a first field to be performed when the first encoded instruction is executed, identify a vulnerable value in a second field within the first encoded instruction, where the vulnerable value includes a second opcode, determine that the first encoded instruction can be replaced with one or more alternative encoded instructions that do not contain the vulnerable value, and replace the first encoded instruction with the one or more alternative encoded instructions.

Compiling techniques for hardening software programs against branching programming exploits

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Santa Clara, CA, United States of America

Dmitry Babokin