Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Dmitriy Vladimirovich Alekseev

Alexei Vladimirovich Galatenko

Alexander Markovic

Elyar Eldarovich Gasanov

Andrey Nikitin

Pavel Anatolyevich Panteleev

Aleksey Alexandrovich Letunovskiy

Ilya Viktorovich Lyalin

Denis Vassilevich Parfenov

Andre P Sokolov

Yuri Shutkin

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

Systems and methods for area efficient data encoding

In one embodiment, a cryptography processor compatible with the Advanced Encryption Standard (AES) for encrypting and decrypting has a memory storing each element of an AES State, normally 8-bit long, in a corresponding memory space that is at least 9 bits long. Using the larger memory spaces, the processor performs modified AES transformations on the State. A modified column-mixing transformation uses bit-shifting and XOR operations, thereby avoiding some multiplications and modulo reductions and resulting in some 9-bit State elements. A modified byte-substitution transformation uses a 512-element look-up table to accommodate 9-bit inputs. The modified byte-substitution transformation is combined with a modified row-shifting transformation. The memory has data registers each holding four State elements. A modified expanded key schedule is used in a modified round-key-adding transformation that is combined with the modified column-mixing transformation, wherein all four elements stored in a single data register are processed together in some operations.

Cryptographic processing using a processor

In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M, i=1, . . . , N, and the processing of each block Mincludes t iterations of processing words of message schedule {W}. In each iteration possible, the DSP uses free operations to precalculate Wand working variable values for use in the next iteration. In addition, in each iteration possible, the DSP rotates the registers associated with particular working variables to reduce operations that merely copy unchanged values from one register to another.

Hash processing using a processor

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Moscow, Russia

Dmitriy Vladimirovich Alekseev