Intel Corporation

Dmitri Vainbrand

Michael Behar

Ehud Cohen

Gal Leibovich

Bharat Daga

Gal Novik

Oren Agam

Ajit Singh

Daniel David Ben-Dayan Rubin

Yonatan Glesner

Methods and apparatus relating to techniques for incremental network quantization. In an example, an apparatus comprises logic, at least partially comprising hardware logic to determine a plurality of weights for a layer of a convolutional neural network (CNN) comprising a plurality of kernels; organize the plurality of weights into a plurality of clusters for the plurality of kernels; and apply a K-means compression algorithm to each of the plurality of clusters. Other embodiments are also disclosed and claimed.

Per kernel Kmeans compression for neural networks

Embodiments described herein provide a processing apparatus comprising compute logic to generate output feature map data for a convolutional neural network (CNN) and write the feature map data to a memory buffer; a direct memory access (DMA) controller including a feature map encoder, the DMA controller to read the feature map data from the memory buffer, encode the feature map data using one of multiple encode algorithms, and write encoded feature map data to memory coupled with the processing apparatus; and wherein the compute logic is to read the encoded feature map data from the memory in an encoded format and decode the encoded feature map data while reading the encoded feature map data.

System and method of encoding and decoding feature maps and weights for a convolutional neural network

A processor, including: decode circuitry to decode instructions; a data cache unit including circuitry to cache data for the processor; and an approximate matrix multiplication (AMM) circuit including: a data receptor circuit to receive a weight vector w and an input vector x, both of size N, and a compression regulating parameter n; a factorizer circuit to factorize w into w&#x2245;B&#xb7;s, by computing a binary factorized matrix B of size N&#xd7;n, and a dictionary vector s of size n; and a binary multiplier circuit to compute w^T x&#x2245;(B&#xb7;s)^T x=s^T(B^T x), the binary multiplier circuit comprising a hardware accelerator circuit to compute an array productB^T x).

Binary multiplier for binary vector factorization

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Sunnyvale, CA, United States of America

Dmitri Vainbrand