Silicon Storage Technology, Inc.

University of California

Denso Corporation

Dmitri Strukov

Farnood Merrikh Bayat

Xinjie Guo

Hieu Van Tran

Nhan Do

Vipin Tiwari

Mark Reiten

Irina Kataeva

Mohammad Reza Mahmoodi

Farnood Merrikh-Bayat

Mirko Prezioso

Hussein Nili Ahmadabadi

Zahra Fahimi

Farnood Merrik-Bayat

Brian Hoskins

Mohammad Bavandpour

A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

Memory device of non-volatile memory cells

An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Deep learning neural network classifier using non-volatile memory array

Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

Output circuitry for non-volatile memory array in neural network

Building blocks for implementing Vector-by-Matrix Multiplication (VMM) are implemented with analog circuitry including non-volatile memory devices (flash transistors) and using in-memory computation. In one example, improved performance and more accurate VMM is achieved in arrays including multi-gate flash transistors when computation uses a control gate or the combination of control gate and word line (instead of using the word line alone). In another example, very fast weight programming of the arrays is achieved using a novel programming protocol. In yet another example, higher density and faster array programming is achieved when the gate(s) responsible for erasing devices, or the source line, are re-routed across different rows, e.g., in a zigzag form. In yet another embodiment a neural network is provided with nonlinear synaptic weights implemented with nonvolatile memory devices.

Mixed signal neuromorphic computing with nonvolatile memory devices

Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

Summing circuit for neural network

Numerous examples are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one example, a circuit comprises a digital-to-analog converter to convert a target weight comprising digital bits into a target voltage, a current-to-voltage converter to convert an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator to compare the output voltage to the target voltage during a verify operation.

Verification of a weight stored in a non-volatile memory cell in a neural network following a programming operation

An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

Programming methods for neural network using non-volatile memory array

Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.

A security primitive for an integrated circuit comprises an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration. The floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs).

Reconfigurable physically unclonable functions based on analog non-volatile memories

A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Flash memory array with individual memory cell read, program and erase

A neural network is implemented as a memristive neuromorphic circuit that includes a neuron circuit and a memristive device connected to the neuron circuit. An input voltage is sensed at a first terminal of a memristive device during a feedforward operation of the neural network. An error voltage is sensed at a second terminal of the memristive device during an error backpropagation operation of the neural network. In accordance with a training rule, a desired conductance change for the memristive device is computed based on the sensed input voltage and the sensed error voltage. Then a training voltage is applied to the memristive device. Here, the training voltage is proportional to a logarithmic value of the desired conductance change.

Growing community of inventors

Goleta, CA, United States of America

Dmitri Strukov