Intel Corporation

Dmitri Loubychev

Mantu K Hudait

Joel Mark Fastenau

Amy W K Liu

Mohamad A Shaheen

Peter G Tolchinsky

Loren A Chow

Suman Datta

Jack T Kavalieros

Aaron A Budrevich

Robert S Chau

A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1&#xd7;10cmto be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Stacking fault and twin blocking barrier for integrating III-V on Si

A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1&#xd7;10cmto be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

Semiconductor buffer architecture for III-V devices on silicon substrates

Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

Buffer layers for device isolation of devices grown on silicon

A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1&#xd7;10cmto be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Dopant confinement in the delta doped layer using a dopant segregration barrier in quantum well structures

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an InAlAs bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InAlAs layer on the InAlAs bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.

Methods of forming buffer layer architecture on silicon and structures formed thereby

Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures

A device grade III-V quantum well structure formed on a silicon substrate using a composite buffer architecture and the method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1&#xd7;10cmto be formed on silicon substrates. In an embodiment of the present invention, an InSb quantum well layer is sandwiched between two larger band gap barrier layers. In an embodiment of the present invention, InSb quantum well layer is strained. In a specific embodiment, the two larger band gap barrier layers are graded.

Dislocation-free InSb quantum well structure on Si using novel buffer architecture

In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.

Buffer architecture formed on a semiconductor wafer

Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

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Bethlehem, PA, United States of America

Dmitri Loubychev