Hypres, Inc.

Seeqc Inc.

Dmitri Kirichenko

Oleg A Mukhanov

Alexander F Kirichenko

A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Low-power biasing networks for superconducting integrated circuits

A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator.

Superconducting analog-to-digital converter with current amplified feedback

A superconducting circuit, and a method, are disclosed for generating pulses with stable frequency. The circuit includes an annular Long Josephson Junction (LJJ) capable of producing electrical pulses of a desired frequency due to a steady bias current applied to the LJJ. The circuit further includes an electrical interface for injecting an RF signal of a first frequency into the annular LJJ, resulting in the desired frequency locking onto the first frequency. Typically the first frequency substantially equals the desired frequency. The injection of the RF signal further results in the decrease of the frequency jitter of the desired frequency. The pulses generated in the loop section of the LJJ are outputted through a tail section of the LJJ, and through transmission lines which couple to the tail section.

Injection locked Long Josephson Junction pulse source

A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an N-order bandpass sigma-delta ADC, with the order 'N' being at least 2. The ADC includes a sequence of stages, which stages include feedback loops and resonators. The ADC further includes active superconducting components which directionally couple resonator pairs of adjacent stages. The active superconducting components electrically shield the higher order resonator from the lower order resonator. These active superconductor components include a superconducting quantum interference device (SQUID) amplifier, which is inductively coupled to the higher order resonator, and may include a Josephson transmission line (JTL), which is configured to electrically connect the SQUID amplifier to the lower order resonator. The first stage of ADC may employ an implicit feedback loop.

Superconductor analog-to-digital converter

A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc.

Multiphase clock for superconducting electronics

A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators.

Superconductor multi-level quantizer

A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an N-order, having N resonators, with N being at least 2. The ADC also may have N&#x2212;1 amplifiers, where the amplifiers directionally couple sequential pairs of the resonators. The ADC further includes a Josephson Junction (JJ) comparator. All N resonators connect in parallel to the JJ comparator, and the JJ comparator is providing an implicit feedback for all N resonators. A method for implementing the sigma-delta ADC without any explicit feedback loops is also disclosed.

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Yorktown Heights, NY, United States of America

Dmitri Kirichenko