Intel Corporation

University of Nebraska

University of Texas System

The State University of New York

Other

University of California

The Johns Hopkins University

Kepler Computing Inc.

Intel Corproation

Dmitri E Nikonov

Ian A Young

Sasikanth Manipatruni

Chia-Ching Lin

Tanay Gosavi

Uygar E Avci

Mario J Paniccia

Kaan Oguz

Andrew Marshall

Tahir Ghani

Brian S Doyle

Robert S Chau

Elijah V Karpov

Christopher J Wiegand

Michael T Morse

Ravi Pillarisetty

Johanna M Swan

Amrita Mathuriya

Ajey Poovannummoottil Jacob

Patrick R Morrow

Robert L Sankman

James S Clarke

Noriyuki Sato

Tanay Karnik

Kevin Lai Lin

Charles C Kuo

Kelin J Kuhn

Robert L Bristol

Ansheng Liu

David J Michalak

David L Kencke

Marko Radosavljevic

Adel A Elsherbini

Rajeev Kumar Dokania

Niloy Mukherjee

Shawna M Liff

Ram K Krishnamurthy

Rafael Rios

Biswajeet Guha

Kevin O'Brien

Ramamoorthy Ramesh

Seiyon Kim

Ikenna Odinaka

Christopher J Jezewski

Shigeki Tomishima

Omesh Tickoo

Achintya K Bhowmik

Daniel Henry Morris

Ilya V Karpov

Andrew J Daiber

George I Bourianoff

Anurag Chaudhry

John J Plombon

Yi Ding

Benjamin Buford

Peter A Dowben

Raseong Kim

Punyashloka Debashis

Hai Li

Jasmeet S Chawla

Michael S Salib

Nishtha Sharma Gaul

Everett X Wang

Ashish Verma Penumatcha

Mark Thomas McCormack

Sou-Chi Chang

Gary Allen

Clifford L Ong

Jonathan Bird

Michael C Mayberry

Krishna Bharath

Gerald S Pasdast

Anders Grunnet-Jepsen

Kang L Wang

Vivek K Singh

Kanwaljit Singh

John N Sweetser

Carl H Naylor

Jun-Fei Zheng

Julien Sebot

Mahesh M Subedar

Neelam Chandwani

Huichu Liu

Robert J Munoz

Eric A Karl

Andrew Alduino

Chytra Pawashe

Nevine Nassif

Thomas Gerard Willis

Kaushik Vaidyanathan

Darrell G Schlom

Jin Pan

Jun Su

Atul A Tambe

C Michael Garner

Sean M Koehl

Shida Tan

Patrick Theofanis

Christian Binek

Carleton L Molnar

A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

Differentially programmable magnetic tunnel junction device and system including same

Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.

Perovskite-based magnetoelectric spin-orbit logic devices

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

Magnetoelectric spin-orbit device with in-plane and perpendicular magnetic layers and method of manufacturing same

A logic gate includes a first capacitor to receive a first input, the first capacitor coupled to a node and a first diode structure coupled to the first input and the node. The logic gate future includes a second capacitor to receive a second input, the second capacitor coupled to the node and a second diode structure coupled to the second input and the node. The logic gate further includes a third capacitor to receive a third input, wherein the third capacitor is coupled to the node and a third diode structure coupled to the third input and the node.

Diode connected non-linear input capacitors based majority gate

In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.

Piezo-resistive resonator device having drive and sense transistors with wells of opposite doping

In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

Spin-orbit readout using transition metal dichalcogenides and proximitized graphene

A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor

Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.

Staged oscillators for neural computing

Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.

Neural computing dies with stacked neural core regions

A neural network scheme is described that uses unsupervised learning in oscillator neural networks. Training occurs by varying the weights in proportion to the output from a frequency detector. Inputs and initial weights are split into plurality of inputs and plurality of weights. These split inputs and weights can be analog or digital. Oscillators generate signals having frequencies that represent difference in inputs, initial weights, and adjusted factors. Frequency detectors are used to compare the oscillator frequencies with a synchronized frequency of all oscillators. The output of the frequency detectors are used to generate the adjusted factors, and in turn generate trained weights.

Oscillator based neural network apparatus

Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

Precise writing of multi-level weights to memory devices for compute-in-memory

An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS, MoSe, WS, WSe, PtS, PtSe, WTe, MoTe, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

Transition metal dichalcogenide based spin orbit torque memory device

Embodiments may relate to a system to be used in an oscillating neural network (ONN). The system may include a control node and a plurality of nodes wirelessly communicatively coupled with a control node. A node of the plurality of nodes may be configured to identify an oscillation frequency of the node based on a weight W and an input X. The node may further be configured to transmit a wireless signal to the control node, wherein a frequency of the wireless signal oscillates based on the identified oscillation frequency. Other embodiments may be described or claimed.

Wireless oscillator neural network

Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

Multi-level spin logic

Growing community of inventors

Beaverton, OR, United States of America

Dmitri E Nikonov