Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Dmitri Borisovich Strukov

Richard Stanley Williams

Alexandre M Bratkovski

Jianhua Yang

Zhiyong Li

Philip John Kuekes

Matthew D Pickett

Shih-Yuan Wang

John Paul Strachan

Wei Guang Wu

Gregory Stuart Snider

Gilberto Medeiros Ribeiro

Yevgeniy Eugene Shteyn

Michael R T Tan

Julien Borghetti

Duncan J Stewart

R Stanley Williams

A multilayer circuit () includes a base layer () which has a number of base vias (), a first overlying layer () formed on the base layer () and having a first routing section () and a second overlying layer () formed on the first overlying layer (). The second overlying layer () has a second routing section () and is formed using the same set of masks. The first routing section () and the second routing section () form a unique electrical pathway () between a base via () and an element in an overlying layer. A method for forming a multilayer circuit is also provided.

Multilayer circuit

A nanoscale switching device has an active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field. The switching device has first, second and third electrodes with nanoscale widths. The active region is disposed between the first and second electrodes. A resistance modifier layer, which has a non-linear voltage-dependent resistance, is disposed between the second and third electrodes.

Nanoscale switching device

A memristive device includes a first electrode; a second electrode; a junction between the first electrode and the second electrode, the junction including a semiconductor matrix and particles embedded in the semiconductor matrix, the particles being configured to hold a selectable level of electrical charge, the electrical charge controlling the amount of current flowing through the junction for a given reading voltage. A method for using a memristive device includes: applying a first voltage across a memristive junction, the memristive junction including a semiconductor matrix and particles embedded in the semiconductor matrix; electrical charges introduced into the semiconductor matrix by the first programming voltage being trapped within the particles; applying a reading voltage across the memristive junction; and measuring a current across the junction, the current being reduced proportionally to the electrical charges trapped within the potential wells, the current being used to determine a state of the junction.

Memristive device based on current modulation by trapped charges

An ionic device includes a layer of an ionic conductor containing first and second species of impurities. The first species of impurity in the layer is mobile in the ionic conductor, and a concentration profile of the first species determines a functional characteristic of the device. The second species of impurity in the layer interacts with the first species within the layer to create a structure that limits mobility of the first species in the layer.

Ionic devices with interacting species

A device contains a first layer, a second layer; and a membrane between the first and second layers. Mobile ions are in at least one of the first and second layers, and the membrane is permeable to the ions. Interfaces of the conductive membrane with the first layer and the second layer are such that charge of a polarity of the ions collects at the interfaces.

Ionic devices containing a membrane between layers

A capacitive crossbar array includes a first set of conductors and a second set of conductors which intersect to form crosspoints. A nonlinear capacitive device is interposed between a first conductor within the first set and a second conductor within the second set at a crosspoint. The nonlinear capacitive device is configured to store information which is accessible through said first conductor and said second conductor. A method for utilizing a capacitive crossbar array is also provided.

Capacitive crossbar arrays

A memristive device is disclosed herein. The device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two mobile species are present in the active region. Each of the at least two mobile species is configured to define a separate state variable of the memristive device.

Memristive device and methods of making and using the same

A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes.

Memristive switch device

Resistive switches and related methods are provided. Such a resistive switch includes an active material in contact with opposite end electrodes. The active material defines electron traps that capture or release charges in accordance with applied switching voltages. Resistive switches are characterized by ON state and OFF state resistance curves. Resistance ratios of ten times or more are exhibited. The state of a resistive switch is determined using sensing voltages lesser then the switching threshold.

Resistive switches

A reconfigurable multilayer circuit () includes a complimentary metal-oxide-semiconductor (CMOS) layer () having control circuitry, logic gates (), and at least two crossbar arrays () which overlie the CMOS layer (). The at least two crossbar arrays () are configured by the control circuitry and form reconfigurable interconnections between the logic gates () within the CMOS layer ().

Reconfigurable multilayer circuit

A memory device () includes a semiconductor wire including a source region (), a drain region (), and a channel region () between the source region () and the drain region (). A gate structure that overlies the channel region includes a memristive portion () and a conductive portion () overlying the memristive portion ().

Memristive transistor memory

A memcapacitive device includes a first electrode having a first end and a second end and a second electrode. The device has a memcapacitive matrix interposed between the first electrode and the second electrode. The memcapacitive matrix has a non-linear capacitance with respect to a voltage across the first electrode and the second electrode. The memcapacitive matrix is configured to alter a signal applied on the first end by at least one of a) changing at least one of a rise-time and a fall-time of the signal and b) delaying the transmission of the signal based on the application of a programming voltage across the first electrode and the second electrode.

Memcapacitive devices

One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.

Dense nanoscale logic circuitry

A three dimensional multilayer circuit includes a via array made up of a set of first vias and a set of second vias and an area distributed CMOS layer configured to selectively address said first vias and said second vias. At least two crossbar arrays overlay the area distributed CMOS layer. These crossbar arrays include a plurality of intersecting crossbar segments and programmable crosspoint devices which are interposed between the intersecting crossbar segments. The vias are connected to the crossbar segments such that each programmable crosspoint devices can be uniquely accessed using a first via and a second via.

Three dimensional multilayer circuit

A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.

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Mountain View, CA, United States of America

Dmitri Borisovich Strukov