Finisar Corporation

Visa International Service Association

Dmitri Bannikov

Serguei Dorofeev

Alex Fishman

Robert Lee Fennelly

Andreas G Weber

Subra Nagarajan

Samantha R Bench

Konstantinos G Haritos

Paul Sung

Rudolf J Hofmeister

Payman Mohassel

Shashank Agrawal

Sanjeev Sharma

Gaven James Watson

Atul Luykx

Sergey Smirnoff

Ruldolf J Hofmeister

Chonghua Zhou

Denis Y Lefebvre

Alexander Fishman

Manjush Menon

Selvaganesh Vasudevan

Systems, methods, and computer readable media are provided for improving the usability of a cryptogram generated in a first cryptographic protocol such as triple-DES. The methods may generate a first cryptogram using a first identifier in a first cryptographic protocol, stored in a key store within an insecure memory of the mobile communication device, generate, within a secure memory of the mobile communication device, a second cryptogram using a second identifier in a second cryptographic protocol, stored in the secure memory, combining, the first cryptogram and a number of characters of the second cryptogram equal to the length of the first cryptogram to generate a third cryptogram and transmitting the third cryptogram to an payment processing network to validate a transaction. A transaction associated with the third cryptogram may be validated by an authorization entity or an issue entity.

Mobile payments using multiple cryptographic protocols

Unknown devices may be bound to an identity using a four step process that involves trusted relationships only between known partner entities and a known user attribute. The identity may be an account, such as a personal account number (PAN). The PAN may be abstracted using a token for use with the device. The unknown device may first be enrolled at a service to establish a cryptographically verifiable identity. A binding request for the enrolled device may be sent to an issuer of the PAN resulting in the issuer generating a challenge. After a successful authentication of the challenge at the token service provider, the binding of the token to the device is complete.

Enhanced consumer device validation

One example of a test board includes first and second communication ports configured for communication with a master device and a DUT, respectively. A bit error rate tester of the test board is arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester includes at least one IC whose maximum data rate is temperature sensitive. Finally, the test board includes a temperature control system arranged to control the IC temperature so that a maximum data rate of the IC can be adjusted through the use of thermal effects.

Temperature control in an integrated circuit

Systems and methods are provided for configuring an optoelectronic device so as to control various operating conditions at various temperatures. The method includes operating the optoelectronic device at a first temperature, adjusting a first control parameter of the optoelectronic device to satisfy a first operating requirement and recording an associated first value of the first control parameter. Further, the method includes operating the optoelectronic device at a second temperature, adjusting the first control parameter of the optoelectronic device to satisfy the first operating requirement, and recording an associated second value of the first control parameter. From the first and second recorded values of the first control parameter, a sequence of values for the first control parameter for a corresponding sequence of temperatures in a predefined range of temperatures is determined and stored in a programmable device within the device. In addition, one or more control parameters may be adjusted at each temperature to satisfy one or more operating requirements.

Temperature and jitter compensation controller circuit and method for fiber optics device

An exemplary optoelectronic transceiverincorporating features of the present invention is shown in FIGS.and. The transceivercontains a receiver circuit, a transmitter circuit, a power supply voltageand ground connections. The receiver circuit of the transceiver includes a Receiver Optical Subassembly (ROSA), which may contain a mechanical fiber receptacle as well as a photodiode and pre-amplifier (preamp) circuit. The ROSAis in turn connected to a post-amplifier (postamp) integrated circuit, the function of which is to generate a fixed output swing digital signal which is connected to outside circuitry via the RX+ and RX&#x2212; pins. The postamp circuitalso often provides a digital output signal known as Signal Detect or Loss of Signal indicating the presence or absence of suitably strong optical input. The postamp circuitdoes not necessarily have to be used to generate the Signal Detect or Loss of signal. In alternative embodiments, the postamp circuitcould be replaced with a CDR ('Clock Data Recovery') or a demux chip, which embodiments are not shown.

Systems and methods are disclosed measuring the turn-on and turn-off times of an optoelectronic transceiver's transmitter circuitry. The method includes generating a two bit sequences from separate bit sequence generators using the same controlling pattern. The first bit sequence is transmitted through an optoelectronic device and compared with corresponding bit groups in the second bit sequence. The optoelectronic device is disabled and a count of compared bit groups is kept until the comparison indicates that the optoelectronic device is completely off. Using the count and one or more of the bit groups, a turn-off time is calculated. Alternatively, the method is used to calculate a turn-on time. The optoelectronic device is enabled and a count is kept from the time the device is enabled to when the comparison of the corresponding bit groups indicates that the optoelectronic device is completely on.

System and method of measuring turn-on and turn-off times of an optoelectronic device

The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiver circuitry. Data generated by a BERT is transmitted in an electrical form to a DUT and a master device. The DUT transmits data received in an electrical form to the master device in an optical form and the master device transmits data received in an electrical form to the DUT in an optical form. The master device and the DUT then transmit data received in an optical form back to the BERT in an electrical form. The data received from the DUT and the master device, respectively, is separately tested for bit errors. Do so enables to calculation of bit error rates for two distinguishable data paths through the DUT.

System and method of detecting a bit processing error

The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to measure a signal propagation delay through an object connected to an optoelectronic device. The present invention includes determining for how long after a specific bit or bit group is transmitted by an optical transceiver the bit or bit group is received at the other end of the object connected to the optical transceiver.

System and method of measuring a signal propagation delay

A system and method for testing the jitter tolerance and signal attenuation tolerance of an optoelectronic device is disclosed. The system includes a generation circuit, delay circuit and comparison circuitry. A first sequence of bits is generated, delayed, and sent to the optoelectronic device. The optoelectronic device receives the bits and retransmits them as a second sequence to the comparison circuitry, which compares the two bit sequences to determine a bit error rate. The bit error rate is then used to determine the jitter tolerance and, in an alternate embodiment, the signal attenuation tolerance of the optoelectronic device being tested.

System and method of testing a transceiver

Systems and methods for testing bit processing capacities of electronic devices and for reducing or eliminating jitter that compromises the ability of electronic devices to perform this task. Embodiments include circuitry and a methodology for locating and employing a data signal delay&#x2014;in conjunction with a latch&#x2014;to reduce or eliminate jitter from serial encoded data generated by a serializer/deserializer. The data signal delay ensures that the latch latches a state of the serial encoded data at a position within a data signal cycle of minimum jitter.

Growing community of inventors

Mountain View, CA, United States of America

Dmitri Bannikov