Micron Technology Incorporated

Lodestar Licensing Group LLC

Dmitri A Yudanov

Sean Stephen Eilert

Samuel E Bradshaw

Ameen D Akel

Shanky Kumar Jain

Kenneth Marion Curewitz

Sivagnanam Parthasarathy

Hernan Adolfo Castro

Shivasankar Gunasekaran

William A Melton

Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

Signal development caching in a memory device

In a mobile device, processes of an application can be monitored and scored for initial data distribution. Specifically, a method can include monitoring processes of an application, and scoring objects or components used by the processes to determine placement of the objects or components in memory during initiation of the application. The method can also include, during initiation of the application, loading, into a first portion of the memory, at least partially, the objects or components scored at a first level. The method can also include, during initiation of the application, loading, into a second portion of the memory, at least partially, the objects or components scored at a second level. The objects or components scored at the second level can be less critical to the application than the objects or components scored at the first level.

Initial data distribution for different application processes

Systems, methods and apparatuses of Artificial Neural Network (ANN) applications implemented via Memory as a Service (MaaS) are described. For example, a computing system can include a computing device and a remote device. The computing device can borrow memory from the remote device over a wired or wireless network. Through the borrowed memory, the computing device and the remote device can collaborate with each other in storing an artificial neural network and in processing based on the artificial neural network. Some layers of the artificial neural network can be stored in the memory loaned by the remote device to the computing device. The remote device can perform the computation of the layers stored in the borrowed memory on behalf of the computing device. When the network connection degrades, the computing device can use an alternative module to function as a substitute of the layers stored in the borrowed memory.

Memory as a service for artificial neural network (ANN) applications

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

Read broadcast operations associated with a memory device

The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.

Parallel processing in a spiking neural network

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Methods for performing processing-in-memory operations, and related systems

Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.

Inter operating system memory services over communication network connections

Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

Matching patterns in memory arrays

A memory module having a plurality of memory chips, at least one controller (e.g., a central processing unit or special-purpose controller), and at least one interface device configured to communicate input and output data for the memory module. The input and output data bypasses at least one processor (e.g., a central processing unit) of a computing device in which the memory module is installed. And, the at least one interface device can be configured to communicate the input and output data to at least one other memory module in the computing device. Also, the memory module can be one module in a plurality of memory modules of a memory module system.

Memory module with computation capability

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

Write broadcast operations associated with a memory device

Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.

Customized root processes for groups of applications

The present disclosure is directed to a distributed graphics processor unit (GPU) architecture that includes an array of processing nodes. Each processing node may include a GPU node that is coupled to its own fast memory unit and its own storage unit. The fast memory unit and storage unit may be integrated into a single unit or may be separately coupled to the GPU node. The processing node may have its fast memory unit coupled to both the GPU node and the storage node. The various architectures provide a GPU-based system that may be treated as a storage unit, such as solid state drive (SSD) that performs onboard processing to perform memory-oriented operations. In this respect, the system may be viewed as a 'smart drive' for big-data near-storage processing.

Distributed graphics processor unit architecture

Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

Methods of performing processing-in-memory operations, and related devices and systems

Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

Growing community of inventors

Rancho Cordova, CA, United States of America

Dmitri A Yudanov