International Business Machines Corporation

Globalfoundries Inc.

Diyanesh B Chinnakkonda Vidyapoornachary

Saravanan Sethuraman

Marc Avery Gollub

Tony Emile Sawan

Edgar Rolando Cordero

Gary A Tressler

Kyu-hyoun Kim

Anil Bindu Lingambudi

Timothy Jay Dell

Anand Haridass

Arun Joseph

Girisankar Paulraj

Warren Edward Maule

Saritha Arunkumar

David Michael Daly

Arindam Raychaudhuri

Joab Daniel Henderson

Sridhar H Rangarajan

Ray Clement Laning

Kirk David Peterson

Kenneth Lee Wright

Stephen P Glancy

John B DeForge

Saurabh Chadha

Daniel Lewis

Douglas J Cowie

Michael D Pardeik

Robert K Montoye

Hillery C Hunter

Charles Robert Lefurgy

Prasanna Jayaraman

Charles Arthur Kilmer

Brad William Michael

Srinivas Bangalore Purushotham

Vijay Anand Mathiyalagan

Spandana V Rachamalla

Preetham H Raghavendra

Vipin Patel

Adam J McPadden

Anuwat Saetow

Vidhya Shankar Venkatesan

Nagendra K Gurram

Jeremy R Neaton

Sumantra Sarkar

Sean Dalton

Rocio Yolanda Garza

Farheen Munshi

In an example, a computer system includes: a hardware platform including a processor, system memory, and a plurality of input/output (IO) devices, the processor including a controller having a trace and optimize function controller (TOF); and a software platform including an operating system (OS) executing on the hardware platform; wherein the TOF is configured to communicate with the processor, the system memory, and the plurality of IO devices to obtain current settings thereof and to determine final settings for the processor, the system memory, and the plurality of IO devices based on the current settings; and wherein the controller is configured to control the processor, the system memory, and the plurality of IO devices based on the final settings.

System parameter trace and test coverage optimization in a computer system

Embodiments relate to monitoring computing hardware in a computing infrastructure facility. Image data and environmental data are received and a current operational status for a computing hardware component is determined from the image data. A hardware operational status tracking model and environment tracking model for the computing hardware component are updated. Embodiments can perform a root cause analysis if the current operational status is a fault status to determine if the fault status was caused by environmental conditions.

System to monitor computing hardware in a computing infrastructure facility

A circuit-cycle fault reproduction system includes a hardware processor configured to execute at least one computing cycle corresponding to a given number instructions. A cycle tracking unit is configured to identify at least one test cycle included in a range of computing cycles starting from at a start cycle and completing at an end cycle. A fail cycle detection unit is in signal communication with the cycle tracking unit. The fail cycle detection unit is configured to identify a failed cycle among the plurality of test cycles based on a cycle difference between the starting cycle and the ending cycle, and to actively modify the range of computing cycles based on a comparison between the cycle difference and a cycle difference threshold value.

Circuit-cycle reproduction

A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

Instruction level tracing for analyzing processor failure

Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Thermally aware memory management

An apparatus for core repair includes a failure analysis and recovery ('FAR') probe that accesses a core of a processor and units of the core over a low-level communication bus while the core is operational after a failure notification. The FAR probe compares operational data of the core versus vital product data ('VPD') while the core is running tests and a thermal, power, functional (&#x201c;TPF&#x201d;) workload to determine if the core is in a degraded state and runs tests to identify a failure after determining that the core is in a degraded state. The FAR probe adjusts parameters of the core in response to identifying a failure of the core and re-evaluates the core to determine if the core is functional. The FAR probe returns the core to service after determining that the core is functional. The FAR probe operates independent of other processor cores while the cores are operational.

Core repair with failure analysis and recovery probe

A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.

Managing heterogeneous memory resource within a computing system

Embodiments of the present invention include detecting one or more memory modules coupled to a memory controller via a memory channel. A total power requirement for the one or more memory modules is determined. A voltage regulator module set point of the memory channel is adjusted based at least in part on the power requirement for the one or more memory modules. The voltage regulator module provides power to the memory modules and is characterized by an optimal load current value where the voltage regulator module operates at a peak efficiency. An operating mode of the memory controller is determined. Based on determining that the memory controller is operating in a first mode, the commands serviced by the one or more memory modules are throttled by the memory controller to keep a load current of the memory channel within a range of the optimal load current value.

Memory subsystem power management

A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

Leakage power characterization at high temperatures for an integrated circuit

A method and a system for monitoring conditions of offline storage devices is disclosed. Predetermined environmental conditions are monitored to determine whether a storage device should be brought online to perform a data integrity check process. The process receives a triggering event that corresponds with the storage device, powers on the storage devices, selects a page from the storage device, and determines a bit error rate. Once the bit error rate is determined, error-correcting code runs to correct the errors. Any uncorrectable errors are reported, and the storage device is brought back offline.

Data retention in storage drives

Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Optimizing error correcting code in three-dimensional stacked memory

Methods that can manage power for memory subsystems are provided. One method includes providing power to a set of memory devices via a set of power modules, determining a first amount of power being consumed by the set of memory devices, and in response to a predetermined event, modifying a second amount of power provided to the set of memory devices via a set of spare power modules. Systems and apparatuses that can include, perform, and/or implement the method are also provided.

Power management for memory subsystems

An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Autonomous dram scrub and error counting

According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.

Bank-level fault management in a memory system

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Selective error coding

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Bengaluru, India

Diyanesh B Chinnakkonda Vidyapoornachary