Gowin Semiconductor Corporation

Other

Diwakar Chopperla

Jinghui Zhu

Chienkuang Chen

Ning Song

San-Ta Kow

Jianhua Liu

Xiaozhi Lin

Tianping Wang

Zhenyu Gu

Tianxin Wang

Tun Jun Gao

A programmable semiconductor system includes a programmable integrated circuit ('PIC') and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Method and system for enhancing programmability of a field programmable gate array

A hybrid mode system containing an external device and a field-programmable gate array ('FPGA') capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.

Method and system for providing configuration data to a field-programmable gate array via multiple protocol modes

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Method and system for organizing programmable semiconductor device into multiple clock regions

A programmable semiconductor system includes a programmable integrated circuit ('PIC') and storage capable of facilitating a multi-boot with backup default configuration ('MBC') process. The PIC, in one embodiment, includes configurable logic blocks (&#x201c;LBs&#x201d;), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (&#x201c;BDP&#x201d;) containing default configuration data (&#x201c;DCD&#x201d;) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Method and system for enhancing programmability of a field-programmable gate array

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions

A programmable semiconductor system includes a programmable integrated circuit ('PIC') and storage capable of facilitating a multi-boot with backup default configuration ('MBC') process. The PIC, in one embodiment, includes a dual-mode port (&#x201c;DMP&#x201d;), configurable logic blocks (&#x201c;LBs&#x201d;), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Method and system for enhancing programmability of a field-programmable gate array via a dual-mode port

A field-programmable gate array ('FPGA') contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals ('RCSs') generated from a clock source with a high clock signal quality (&#x201c;CSQ&#x201d;) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (&#x201c;NCSs&#x201d;) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (&#x201c;SCSs&#x201d;) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions

The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

System level integrated circuit chip

A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

Secrecy system and decryption method of on-chip data stream of nonvolatile FPGA

The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.

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Fremont, CA, United States of America

Diwakar Chopperla