Texas Instruments Corporation

Divyasree J

Anant Shankar Kamath

Krishnamurthy Ganapathi Shankar

Ashish Ojha

Siddhartha Gopal Krishna

Venkata Naresh Kotikelapudi

Sarangan Thirumavalavan

A circuit includes a first transistor, a second transistor, and a sense transistor. The first current terminals of the first and second transistors are coupled together at a power supply node. The control terminals of the second and third transistors are coupled together. The second current terminals of the first, second, and third transistors are coupled together. The sense resistor is coupled between the first current terminals of the first and second transistors and the first current terminal of the third transistor. The first and second transistors are configured such that during a first mode of operation, current to a load flows through the first and second transistors, and during a second mode of operation, current to a load is discontinued through the first transistor yet flows through the second transistor.

Over-current protection circuit

A circuit includes an input terminal, a first transistor, a second transistor, a comparator, a voltage reference circuit, and a control circuit. The first transistor includes a first terminal coupled to the input terminal. The second transistor includes a first terminal coupled to the input terminal. The comparator includes a first terminal coupled to the input terminal. The voltage reference circuit is coupled to a second terminal of the comparator. The control circuit includes an input, a first output, and a second output. The input is coupled to an output of the comparator. The first output is coupled to a second terminal of the first transistor. The second output is coupled to a second terminal of the second transistor.

Open load detection circuits

One example includes a communication system. The system includes a data transmitter configured to generate a digital communication signal and a data receiver configured to receive the digital communication signal. The system also includes a pulse-width distortion (PWD) correction circuit arranged between the data transmitter and the data receiver and being configured to adjust at least one timing parameter associated with the communication signal.

Timing correction in a communication system

An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency f. The FLL control loop includes a switched capacitor resistor divider that converts fto a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

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Divyasree J