Cadence Design Systems, Inc.

Divyank Mittal

Vivek Chickermane

Rajesh Khurana

Sagar Kumar

Balveer Singh Koranga

An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

IC chip test engine

Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

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Uttar Pradesh, India

Divyank Mittal